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28F128 Datasheet(PDF) 30 Page - Intel Corporation |
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28F128 Datasheet(HTML) 30 Page - Intel Corporation |
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30 / 58 page ![]() 28F128J3A, 28F640J3A, 28F320J3A 24 Preliminary 4.9 Byte/Word Program Commands Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 40H or alternate 10H) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8, “Byte/Word Program Flowchart” on page 31). The CPU can detect the completion of the program event by analyzing the STS pin or status register bit SR.7. When program is complete, status register bit SR.4 should be checked. If a program error is detected, the status register should be cleared. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. The CUI remains in read status register mode until it receives another command. Reliable byte/word programs can only occur when VCC and VPEN are valid. If a byte/word program is attempted while VPEN ≤ VPENLK, status register bits SR.4 and SR.3 will be set to “1.” Successful byte/word programs require that the corresponding block lock-bit be cleared. If a byte/ word program is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set to “1.” 4.10 Program Suspend Command The Program Suspend command allows program interruption to read data in other flash memory locations. Once the programming process starts (either by initiating a write to buffer or byte/word program operation), writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Program Suspend command is written. Polling status register bits SR.7 can determine when the programming operation has been suspended. When SR.7 = 1, SR.2 should also be set to “1”, indicating that the device is in the program suspend mode. STS in level RY/BY# mode will also transition to VOH. Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while programming is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. Status register bits SR.2 and SR.7 will automatically clear and STS in RY/BY# mode will return to VOL. After the Program Resume command is written, the device automatically outputs status register data when read. VPEN must remain at VPENH and VCC must remain at valid VCC levels (the same VPEN and VCC levels used for programming) while in program suspend mode. Refer to Figure 9, “Program Suspend/Resume Flowchart” on page 32. 4.11 Set Read Configuration Command This command is not support on this product. This device will default to the asynchronous page mode. If this command is given to the device it will not effect the operation of the device. |
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