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82375EB Datasheet(PDF) 81 Page - Intel Corporation |
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82375EB Datasheet(HTML) 81 Page - Intel Corporation |
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81 / 131 page  82375EBSB 51103 PCEB Target Termination Conditions As a target the PCEB terminates a transaction due to the following conditions Disconnect When a target the PCEB always responds with a disconnect to a multiple data phase transaction (see the Incremental Latency Timer section) Retry When the pending PCI cycle initiates buffer management activity When the PCEB is locked as a resource and a PCI master tries to access the PCEB without negating the PLOCK signal in the address phase When the EISA Bus is occupied by an EISAISA master or DMA Target Abort The PCEB never generates a target abort 51104 PCEB Master Termination Conditions As an initiator the PCEB terminates a transaction due to the following conditions Completion termination is always used by the PCEB signaling to the target that the PCEB is ready to complete the final data phase of the transaction Master abort termination is issued if the PCEB does not receive a DEVSEL from a target within five PCICLK’s after FRAME assertion The PCEB sets the Received Master Abort Status bit in the PCI Status Register to a 1 Master initiated termination (disconnect) due to Master Latency Timer expiration when the PCEB’s PCI Bus grant is removed (internal PCEBGNT negated) 51105 PCEB ResponsesResults Of Termination PCEB’s response as a target to a master termination Completion termination is the normal way of terminating a transaction If a PCI initiator times out due to LT time-out and ends the current transaction the PCEB cannot detect a difference between normal completion termination and time-out forced termination PCEB’s response as a master to target termination If the PCEB receives a target abort it means that the target device is not capable of handling the transac- tion The PCEB does not try the cycle again If an EISAISA master or the DMA is waiting for the PCI cycle to terminate (EXRDY negated) the target abort condition causes the PCEB to assert EXRDY to terminate the EISA cycle Note that write data is lost and the read data is meaningless This is identical to the way an unclaimed cycle is handled on the ‘‘normally ready’’ EISA Bus If the Line Buffer is the requester of the PCI transaction the target abort mechanism ends the PCI cycle but no valid data transfers are performed into or out of the Line Buffer The Line Buffer does not try the cycle again The Received Target Abort Status bit in the PCI Status Register is set to 1 indicating that the PCEB experienced a target abort condition If the PCEB is retried as an initiator on the PCI Bus it will remove it’s request for 2 PCI clocks before asserting it again to retry the cycle 81 |
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