82375EB datasheet(96/131 Pages) INTEL

96 / 131 page

82375EBSB

547 PCI ARBITRATION AND PCEBESC EISA OWNERSHIP EXCHANGE

There are two aspects of PCEBESC EISA Bus ownership exchange that are explained in this section They

are related to GAT mode and RESUMERETRY operations

The PCEB is the default owner of the EISA Bus When control of the EISA Bus is given to the ESC all PCI

operations targeted to the EISA subsystem (including the PCEB) are retried Retry causes assertion of the

PEREQ

INTA

signal with PEREQ

semantics In this way the PCEB indicates to the ESC that it needs to

obtain ownership of the EISA Bus

5471 GAT Mode And PEREQ

Signaling

In GAT mode the PCEB owns the PCI Bus on behalf of the EISA master and other PCI agents (eg the Host

PCI Bridge) can not generate PCI cycles Therefore the PCEB never generates a back-off (ie retry) as long

as the EISA Bus is controlled by the ESC This might cause starvation of the PCI agents (including the Host

PCI Bridge ie CPU) even in the case of a moderately loaded EISA subsystem The solution is that PEREQ

in the GAT mode is generated when any of the PCI Bus request signals are asserted For particular HostPCI

Bridge designs (eg PCMC) this will be not be an adequate solution since their PCI request can be activated

only based on the CPU generated cycle directed to PCI This will not be possible since the Host Bus (CPU bus)

in the GAT mode is controlled by the HostPCI Bridge and not by the CPU The solution to this type of design

is to generate PEREQ

immediately after entering the GAT mode This feature is controlled via ARBCON

5472 PCI Retry And EISA Latency Timer (ELT) Mechanism

When a PCI cycle is retried by the PCEB (in non-GAT mode) because the EISA Bus is controlled by the ESC

(EISAHLDA asserted) an internal flag is set for the corresponding PCI master This flag masks the request of

a particular master until the PCEB acquires the ownership of EISA and the RESUME condition clears the flag

If the PCI master which is now unmasked does not acquire the ownership of the PCI Bus within the time

period before ESC asserts EISAHOLD again the EISA Bus can be surrendered to the ESC Unmasked

masters will eventually gain the access to the PCI Bus but the EISA Bus will not be available and the master

will be retried again This scenario can be repeated multiple times with one or more PCI masters and starvation

will occur

To solve this situation the PCEB arbitration logic incorporates an EISA Latency Timer mechanism This

mechanism is based on the programmable timer that is started each time that the ESC requires the bus

(EISAHOLD asserted) and there is a PCI agent that has been previously retried because of activity on the

EISA Bus As soon as the ELT timer expires any PCI cycle which is currently in progress is retried and the

EISA Bus is given back to the ESC after the current PCI-to-EISA transaction completes If all the PCI request-

ers masked because of EISAHLDA are serviced before the ELT timer expires the EISA Bus is immediately

surrendered to the ESC The ELT provides a minimum time slice for PCI masters to access the EISA bus even

if EISA masters ISA masters or DMA devices are attempting to acquire the EISA bus

Generally the ELT is set to a larger value if latency sensitive PCI masters which typically access EISA are

present in the system Larger ELT values however do increase the worst case latency for EISA devices which

typically access devices on PCI (eg main memory)

The EISA Latency Timer (ELT) is controlled by the ELTCR Register The value written into ELTCR is system

dependent It is typically between 1 and 3 ms

82375EB Datasheet(PDF) 96 Page - Intel Corporation

82375EB Datasheet(HTML) 96 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL