82375EB datasheet(58/131 Pages) INTEL

58 / 131 page

82375EBSB

Table 4 EISA Resident IDE Registers

(Continued)

Address

(hex)

Addess (Bits)

Access

Type

FEDC

BA98

7654

3210

01F4h

0000

0001

1111

0100

Primary Cylinder Low Register

01F5h

0000

0001

1111

0101

Primary Cylinder High Register

01F6h

0000

0001

1111

0110

Primary Drivehead Register

01F7h

0000

0001

1111

0111

Primary Status Register

0376h

0000

0011

0111

0110

Secondary Alternate Status Register

0377h

0000

0011

0111

Secondary Drive Address Register

03F6h

0000

0011

1111

0110

Primary Alternate Status Register

03F7h

0000

0011

1111

0111

Primary Drive Address Register

42 EISA Cycle Address Decoding

For EISA Bus cycles the PCEB address decoder determines the destination of EISAISA master and DMA

cycles This decoder provides the following functions

Positively decodes memory and IO addresses that have been programmed into the PCEB for forwarding

to the PCI Bus This includes accesses to devices that reside directly on the PCI (memory Regions 41

and IO Regions 41 ) and segments of main memory that resides behind the HostPCI Bridge

Provides access attributes for memory Regions 41 These attributes are used to select the most optimum

access mode (buffered or non-buffered)

All cycles that are not positively decoded to be forwarded to PCI are contained within EISA

NOTE

The registers that reside in the PCEB (configuration registers and BIOS Timer) are not accessible

from the EISA Bus

421 POSITIVELY DECODED MEMORY CYCLES TO MAIN MEMORY

The EISAISA master or DMA addresses that are positively decoded by the PCEB are forwarded to the PCI

Bus If the address is not positively decoded by the PCEB the cycle is not forwarded to the PCI Bus Subtrac-

tive and negative (82374SB only) decoding are not used on the EISA Bus

The PCEB permits several EISA memory address ranges (items a-i) to be positively decoded EISA Bus cycles

to these regions are forwarded to the PCI Bus Regions described by a-f and h are fixed and can be enabled or

disabled independently These regions are controlled by the EADC1 and EADC2 Registers

The region described by g defines a space starting at 1 MByte with a programmable upper boundary of

4 GByte - 2 MByte Within this region a hole can be opened Its size and location are programmable to allow a

hole to be opened in memory space (for a frame buffer on the EISA Bus for example) The size of this region

and the hole are controlled by the MCSTOM MCSBOH and MCSTOH Registers If a hole in main memory is

defined then accesses to that address range are contained within EISA unless defined by the EISA-to-PCI

memory regions as a PCI destined access (See next section)

82375EB Datasheet(PDF) 58 Page - Intel Corporation

82375EB Datasheet(HTML) 58 Page - Intel Corporation

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