82375EB datasheet(44/131 Pages) INTEL

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82375EBSB

Bit

Description

Reserved

Top 64 KByte of 16 MByte Memory Space Enable (FF0000 – FFFFFFh)

This memory block is

enabled when this bit is 1 and disabled when this bit is 0

960 KBytes1 MByte Memory Space Enable (0F0000 – 0FFFFFh)

This memory block is enabled

when this bit is 1 and disabled when this bit is 0

944 – 960 KByte Memory Space Enable (0EC000 – 0EFFFFh)

This memory block is enabled when

this bit is 1 and disabled when this bit is 0

928 – 944 KByte Memory Space Enable (0E8000 – 0EBFFFh)

This memory block is enabled when

this bit is 1 and disabled when this bit is 0

912 – 928 KByte Memory Space Enable (0E4000 – 0E7FFFh)

This memory block is enabled when

this bit is 1 and disabled when this bit is 0

896 – 912 KByte Memory Space Enable (0E0000 – 0E3FFFh)

This memory block is enabled when

this bit is 1 and disabled when this bit is 0

3122 EPMRAEISA-TO-PCI MEMORY REGION ATTRIBUTES REGISTER

Address Offset

5Ch

Default value

00h

Attribute

ReadWrite

Size

8 bits

This register defines buffering attributes for EISA accesses to PCI memory regions specified by MEM-

REGN 41 Registers When an EPMRA bit is 1 (and the Line Buffers are enabled via the PCICON Register)

EISA accesses to the corresponding PCI memory region are performed in buffered mode In buffered mode

read prefetching and write postingassembly are enabled When an EPMRA bit is 0 EISA accesses to the

corresponding PCI memory region are performed in non-buffered mode In non-buffered mode a buffer by-

pass path is used to complete the transaction

NOTE

1 Using buffered mode for EISA accesses to PCI memory regions that contain memory-mapped IO

devices can cause unintended side effects In buffered mode strong ordering is not preserved within

a Dword If the order of the writes to an IO device is important non-buffered mode should be used

Also read-prefetch can cause unintended changes of status registers in the memory-mapped IO

device

2 The Line Buffers are typically enabled or disabled during system initialization These buffers should

not be dynamically enableddisabled during runtime Otherwise data coherency can be affected if a

buffer containing valid write data is disabled and then later re-enabled

82375EB Datasheet(PDF) 44 Page - Intel Corporation

82375EB Datasheet(HTML) 44 Page - Intel Corporation

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