82375EB datasheet(54/131 Pages) INTEL

54 / 131 page

82375EBSB

4112 BIOS Memory Space

The BIOS memory space is subtractively decoded BIOS is typically ‘‘shadowed’’ after configuration and

initialization is complete Thus negative decoding is not implemented for accesses to the BIOS EPROM

residing on the expansion bus

The ESC decoder supports BIOS space up to 512 KBytes The standard 128 KByte BIOS memory space is

000E 0000h to 000F FFFFh (top of 1 MByte) and aliased at FFFE 0000h to FFFF FFFFh (top of 4 GByte) and

FFEE 0000h to FFEF FFFFh (top of 4 GByte -1 MByte) These aliased regions account for the CPU reset

vector and the uncertainty of the state of the A20Gate when a software reset occurs

Note that the ESC component contains the BIOS space decoder that provides address aliasing for BIOS at

4 GByte or 4 GByte - 1 MByte by ignoring the LA20 address line

The additional 384 KByte BIOS memory space at FFF8 0000h to FFFD FFFFh is known as the enlarged BIOS

memory space Note that EISA memory (other than BIOS) must not reside within the address range from

4 GByte -15 MByte to 4 GByte - 1 MByte and from 4 GByte - 512 KByte to 4 GByte to avoid conflict with BIOS

space

Since the BIOS device is 8 or 16 bits wide and typically has very long access times PCI burst reads from BIOS

space invoke a disconnect target termination (using the STOP

signal) after the first data transaction in order

to meet the PCI incremental latency guidelines

4113 Subtractively And Negatively Decoded Cycles To EISA

The PCEB uses subtractive and negative (82375SB only) decoding to forward PCI Bus cycles to the EISA Bus

These modes are defined at the beginning of section 40 Bit 0 of the PDCON Register selects between

negative and subtractive decoding

For subtractive decoding on the 82375EB the DEVSEL

sample point (Figure 5) can be configured to two

different settings by programming the PCICON Register If the ‘‘typical’’ point is selected DEVSEL

is sam-

pled at T and if inactive the cycle is forwarded to EISA If the ‘‘slow’’ point is selected DEVSEL

is sampled

at F T and S The sample point should be configured to match the slowest PCI device in the system This

programmable capability (T or S) permits systems to optimize the DEVSEL

time-out latency to the response

capabilities of the PCI devices in the system The sample point selected must accommodate the slowest

device on the PCI Bus Note that when these unclaimed cycles are forwarded to the EISA Bus the PCEB

drives the DEVSEL

active An active MEMCS

always results in an active DEVSEL

on the ‘‘Typical’’

sample point

For subtractive decoding on the 82375SB the DEVSEL

sample point can be configured to two different

settings by programming the PCICON Register (slow and typical)

82375EB Datasheet(PDF) 54 Page - Intel Corporation

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