82375EB datasheet(62/131 Pages) INTEL

62 / 131 page

82375EBSB

424 EXTERNAL EISA-TO-PCI IO ADDRESS DECODER

Since the IO address map may be highly fragmented it is impractical to provide enough programmable

regions to completely define mapping of registers for IO devices on the PCI The PCEB’s input signal pin

PIODEC

can be used if a more complex IO decode scheme is needed PIODEC

complements the

functions of the four PCEB programmable IO regions with external decode logic If PIODEC

is asserted

during an EISA IO cycle the cycle is forwarded to the PCI Bus

If the PIODEC

signal is not used a pull-up resistor is required to provide an inactive signal level

43 Palette DAC Snoop Mechanism

Some advanced graphics EISAISA expansion boards use the pre-DAC VGA pixel data from the VGA Special

Feature Connector and merge it with advanced graphics data (multi-media for example) The merged data is

then run through a replicated palette DAC on the advanced graphics expansion board to create the video

monitor signal The replicated palette DAC is kept coherent by snooping VGA palette DAC writes Snooping

becomes an issue in a system where the VGA controller is placed on the PCI Bus and the snooping graphics

board is on the EISA expansion bus Normally the PCI VGA controller will respond to the palette DAC writes

with DEVSEL

so the PCEB will not propagate the cycle to the EISA Bus using subtractive decoding

The burden for solving this problem is placed on the VGA subsystem residing on the PCI The VGA subsystem

on PCI must have an enabledisable bit associated with palette DAC accesses When this bit is enabled the

PCI VGA device responds in handshake fashion (generates DEVSEL

TRDY

etc) to IO reads and writes

to the palette DAC space

When this bit is disabled the PCI VGA device responds in handshake fashion only to IO reads to palette DAC

space IO writes to the palette DAC space will be snooped (data latched) by the PCI VGA device but the PCI

VGA subsystem will not generate a DEVSEL

In this case the IO write will be forwarded to the EISA Bus by

the PCEB as a result of subtractive decode The PCI VGA device must be able to snoop these cycles in the

minimum EISA cycle time

The state of palette-DAC snooping control bit does not affect IO reads from the palette DAC space Regard-

less of whether this bit is enabled or disabled the PCI VGA device will service the IO reads from the palette

DAC space

50 PCI INTERFACE

The PCEB provides the PCI Interface for the PCI-EISA Bridge The PCEB can be an initiator (master) or target

(slave) on the PCI Bus and supports the basic PCI Bus commands as described in Section 511 PCI Com-

mand Set For EISA-to-PCI transfers the PCEB is a master on the PCI Bus on behalf of the requesting EISA

device An EISA device can read and write either PCI memory or IO space

The PCEB forwards unclaimed PCI Bus cycles to EISA For PCI Bus cycles that are not claimed the PCEB

becomes a slave on the PCI Bus (claiming the cycle via subtractive or negative decoding) and forwards the

cycle to the EISA Bus Note that negative decoding is only used on the 82374SB

This section describes the PCI Bus transactions supported by the PCEB The section also covers the PCI Bus

latency mechanisms in the PCEB that limit a master’s time on the bus and the PCEB support of parity In

addition the PCEB contains PCI Bus arbitration circuitry that supports up to six masters PCI Bus arbitration is

described in Section 54

82375EB Datasheet(PDF) 62 Page - Intel Corporation

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