82375EB datasheet(85/131 Pages) INTEL

85 / 131 page

82375EBSB

54 PCI Bus Arbitration

The PCEB contains a PCI Bus arbiter that supports six PCI Bus mastersThe HostPCI Bridge PCEB and four

other masters The PCEB’s REQ

GNT

signals are internal An external arbiter is not supported Note that

for proper arbiter operation CPUREQ

must be sampled high by the PCEB when PCIRST

makes a low-to-

high transition The internal arbiter contains several features that contribute to system efficiency

Use of the internal RESUME

signal to re-enable a backed-off initiator in order to minimize PCI Bus

thrashing when the PCEB generates a retry

A programmable timer to re-enable retried initiators after a number of PCICLK’s

A programmable PCI Bus lock or PCI resource lock function

The CPU HostPCI can be optionally parked on the PCI Bus

In addition the PCEB has three PCI sideband signals (FLUSHREQ

MEMREQ

and MEMACK ) that are

used to control system buffer coherency and control operations for the Guaranteed Access Time (GAT) mode

541 PCI ARBITER CONFIGURATION

The PCI arbitration priority scheme is programmable through the configuration registers The arbiter consists

of four banks that can be configured so that the six masters to be arranged in a purely rotating priority scheme

one of 24 fixed priority schemes or a hybrid combination (Figure 21)

82375EB Datasheet(PDF) 85 Page - Intel Corporation