82375EB datasheet(94/131 Pages) INTEL

94 / 131 page

82375EBSB

5452 Guaranteed Access Time Mode

When the PCEB’s Guaranteed Access Time Mode is enabled (via the ARBCON Register) MEMREQ

and

MEMACK

are used to guarantee that the ISA 21ms CHRDY specification is not violated Note that EISA’s

25 ms maximum negation time of the EXRDY signal is a subset of the ISA requirement Thus 21 ms satisfies

both bus requirements

When an EISAISA master or DMA slave requests the EISA Bus (MREQ

or DREQ

active) the EISA Bus

the PCI Bus and the memory bus must be arbitrated for and all three must be owned before the EISAISA

master or DMA is granted the EISA Bus The following lists the sequence of events

1 An EISAISA master DMA or refresh logic requests the EISA Bus The ESC asserts EISAHOLD signal to

the PCEB

2 The PCEB completes the present cycle (ie does not accept any new cycle) and gives the bus to the ESC

by floating its EISA interface and asserting EISAHLDA Before giving the bus to the ESC the PCEB checks

to see if it is locked as a PCI resource It can not grant the EISA Bus as long as the PCEB is locked

At this point the PCEB’s EISA-to-PCI Line Buffers and other system buffers (eg HostPCI Bridge buffers)

that are pointing to the PCI Bus are not flushed The reason is that the ESC might request the bus to run a

refresh cycle that does not require buffer flushing This is not known until the EISA arbitration is frozen (after

EISAHLDA is asserted)

3 Depending on whether the pending cycle is a refresh the ESC initiates one of the following two actions

a If the ESC needs to perform a refresh cycle then it asserts NMFLUSH

(an ESC-to-PCEB flush control

signal) The ESC drives the EISA Bus until it completes the refresh cycle and then gives the bus to the

PCEB by negating EISAHOLD

b If the ESC requested the EISA Bus on behalf of the EISA master DMA or ISA master then it asserts

NMFLUSH

and tri-states the EISA Bus If the PCEB is programmed in GAT (Guaranteed Access Time

mode) the MEMREQ

and FLSHREQ

signals are asserted simultaneously to indicate request for

direct access to main memory and a request to flush the system’s posted write buffers pointing towards

the PCI (including the PCEB’s internal buffers) These requirements are necessary to insure that once the

PCI and EISA Buses are dedicated to the PCEB the cycle generated by the PCEB will not require the PCI

or EISA Buses thus creating a deadlock MEMREQ

and FLSHREQ

are asserted as long as the

EISAISA master or DMA owns the EISA Bus

4 Once the HostPCI Bridge has disabled and flushed its posted write buffers and the memory bus is

dedicated to the PCI interface it asserts MEMACK

Other bridges in the system may also need to disable

and flush their posted write buffers pointing towards PCI due to the FLSHREQ

signal This means that

other devices may also generate a MEMACK

All of the MEMACK s need to be ‘‘wire-OR’d’’ When the

PCEB receives MEMACK

it assumes that all of the critical posted write buffers in the system have been

flushed and that the PCEB has direct access to main memory located behind the HostPCI Bridge

5 When MEMACK

is asserted by the PCEB it will request the PCI Bus (internal PCEBREQ

signal) Before

requesting the PCI Bus the PCEB checks to see that the PCI Bus does not have an active lock The PCI

Bus is granted to the PCEB when it wins the bus through the normal arbitration mechanism Once the PCEB

is granted the PCI Bus (internalPCEBGNT ) the PCEB checks to see if PLOCK

is negated before it

grants the EISA Bus If the PCI Bus is locked when the PCEB is granted the PCI Bus the PCEB releases the

REQ

signal and waits until the PLOCK

is negated before asserting REQ

again Once the PCEB owns

the PCI Bus (internal PCEBGNT ) and the MEMACK

and MEMREQ

signals are asserted the PCI

arbiter will not grant the PCI Bus to any other PCI master except the PCEB until the PCEB releases its PCI

REQ

line

6 When the PCEB is granted the PCI Bus (internal PCEBGNT ) and LOCK

is inactive it asserts

NMFLUSH

to the ESC and the ESC gives the bus grant to the EISA device

82375EB Datasheet(PDF) 94 Page - Intel Corporation

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