82375EB datasheet(15/131 Pages) INTEL

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82375EBSB

21 PCI Bus Interface Signals

Pin Name

Type

Description

PCICLK

PCI CLOCK

PCICLK provides timing for all transactions on the PCI Bus All other PCI

signals are sampled on the rising edge of PCICLK and all timing parameters are defined

with respect to this edge Frequencies supported by the PCEB range from 25 to

33 MHz

PCIRST

PCI RESET

PCIRST

forces the PCEB into a known state All ts and sts signals

are forced to a high impedance state and the sod signals are allowed to float high

The PCEB negates all GNT

lines to the PCI Bus and the PCEB negates its internal

request The PCEB drives AD 310 CBE 30

and PAR during reset to keep these

signals from floating (depending on the state of CPUREQ

and REQ1

as described

in the following paragraph)

As long as PCIRST

is asserted the PCEB drives the AD 310 signals to keep them

from floating Note that CPUREQ

must be sampled high when PCIRST

is asserted

All PCEB registers are set to their default values PCIRST

may be asynchronous to

PCICLK when asserted or negated Although asynchronous the negation of PCIRST

must be a clean bounce-free edge PCIRST

must be asserted for a minimum 1 ms

and PCICLK must be active during the last 100 ms of the PCIRST

pulse

AD 310

ADDRESS AND DATA

AD 310 is a multiplexed address and data bus During the

first clock of a transaction AD 310 contain a physical address During subsequent

clocks AD 310 contain data

A PCEB bus transaction consists of an address phase followed by one or more data

phases Little-endian byte ordering is used AD 70 define the least significant byte

(LSB) and AD 3124 the most significant byte (MSB) The information contained in the

two low order address bits varies by address space In the IO address space AD 10

are used to provide full byte address In the memory and configuration address space

AD 10 are driven ‘‘00’’ during the address phase The other three encodings are

reserved See Section 50 PCI Interface for more details

When the PCEB is a target AD 310 are inputs during the address phase of a

transaction During the following data phase(s) the PCEB may be asked to supply data

on AD 310 as for a PCI read or accept data as for a PCI write As an Initiator the

PCEB drives a valid address on AD 310 (with exceptions related to AD 10 ) during

the address phase and drives write or latches read data on AD 310 during the data

phase

When PCIRST

is asserted the PCEB drives the AD 310 signals to keep them from

floating In addition the PCEB acts as the central resource responsible for driving the

AD 310 signals when no device owns the PCI Bus and the bus is idle

82375EB Datasheet(PDF) 15 Page - Intel Corporation

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