82375EB datasheet(42/131 Pages) INTEL

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82375EBSB

Bit

Description

0EC000 – 0EFFFFh BIOS Extension WE

1eEnable 0eDisable

0EC000 – 0EFFFFh BIOS Extension RE

1eEnable 0eDisable

0E8000 – 0EBFFFh BIOS Extension WE

1eEnable 0eDisable

0E8000 – 0EBFFFh BIOS Extension RE

1eEnable 0eDisable

0E4000 – 0E7FFFh BIOS Extension WE

1eEnable 0eDisable

0E4000 – 0E7FFFh BIOS Extension RE

1eEnable 0eDisable

0E0000 – 0E3FFFh BIOS Extension WE

1eEnable 0eDisable

0E0000 – 0E3FFFh BIOS Extension RE

1eEnable 0eDisable

3120 PDCONPCI DECODE CONTROL REGISTER

Address Offset

58h

Default Value

00h

Attribute

ReadWrite

Size

8 bits

This register enablesdisables positive decode of PCI accesses to the IDE and 8259 locations residing in the

expansion bus subsystem For the 82374SB this register controls the mode of address decode (subtractive or

negative) for memory cycles on the PCI Bus

Subtractive decoding

PCI memory cycles that are not claimed on the PCI Bus (ie DEVSEL

inactive) are forwarded to the EISA

Bus This is the default on power up

Negative decoding (82374SB Only)

PCI memory cycles that are not mapped to one of the regions defined by A B or C below are immediately

forwarded to the EISA Bus (ie without waiting for DEVSEL

time-out) PCI memory cycles that are decoded

to one of the four programmable PCI memory regions but are not claimed (DEVSEL

negated) are forwarded

to the EISA Bus by subtractive decode

A Main memory locations defined by the MEMCS

mapping (MCSCON MCSBOH MCSTOH MCSTOM

MAR1 MAR2 and MAR3 Registers)

B The enabled Video Frame Buffer region 0A0000 – 0BFFFFh (as indicated by bit 2 of the EADC1 Register)

C The four programmable PCI memory regions (defined by the MEMREGN 41 registers)

NOTE

If there are devices on the PCI that are not mapped into any of the regions defined by A B or C

then negative decoding can not be used

82375EB Datasheet(PDF) 42 Page - Intel Corporation

82375EB Datasheet(HTML) 42 Page - Intel Corporation

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