82375EB datasheet(82/131 Pages) INTEL

82 / 131 page

82375EBSB

If the PCEB is disconnected as an initiator on the PCI Bus it will respond very much as if it had been retried

The difference between retry and disconnect is that the PCEB did not see any data phase for the retry

Disconnect may be generated by a PCI slave when the PCEB is running a burst memory cycle to empty or

to fill one line (16-byte) of the Line Buffers In this case the PCEB may need to finish a multi-data phase

transfer and recycles through arbitration as required for a retry An example is when an EISA agent (EISA

ISA master or DMA) issues a read request that the PCEB translates into a 16 byte prefetch (one line) and

the PCEB is disconnected before the Line Buffer is completely filled

5111 PCI DATA TRANSFERS WITH SPECIFIC BYTE ENABLE COMBINATIONS

Non-Contiguous Combination of Byte Enables

As a master the PCEB might generate non-contiguous combinations of data byte enables because of the

nature of assembly operations in the Line Buffers

As a target the PCEB might need to respond to a non-contiguous combination of data byte enables These

cycles can not be passed directly to the EISA Bus the EISA Bus specification does not allow non-contiguous

combinations of byte enables If this situation occurs the PCEB splits the 32-bit transactions into two 16-bit

transactions by first performing the lower word transfer (indicated by BE1

and BE0 ) and then the upper

word transfer (indicated by BE3

and BE2 )

BE 30

1111

As a master the PCEB might generate this combination of data byte enables during Line Buffer flush opera-

tions (burst write) to optimize the usage of the PCI Bus Correct parity is driven during this transaction on the

PCI Bus

As a target the PCEB might need to respond to this combination of data byte enables If BE 30

1111 the

PCEB completes the transfer by asserting TRDY

and providing parity for read cycles The PCEB does not

forward the cycle to the EISA Bus

52 PCI Bus Latency

The PCI specification provides two mechanisms that limit a master’s time on the bus They ensure predictable

bus acquisitions when other masters are requesting bus access These mechanisms are master-initiated

termination supported by a Master Latency Timer (MLT) and a target-initiated termination (specifically discon-

nect) supported by a target’s incremental latency mechanism

521 MASTER LATENCY TIMER (MLT)

The PCEB has a programmable Master Latency Timer (MLT) The MLT is cleared and suspended when the

PCEB is not asserting FRAME

The MLT is controlled via the MLT Register (see Section 41 PCEB Configu-

ration Registers) When the PCEB as a master asserts FRAME

it enables its MLT to count If the PCEB

completes its transaction (negates FRAME ) before the count expires the MLT is ignored If the count

expires before the transaction completes (count e number clocks programmed into the MLT Register ) the

PCEB initiates a transaction termination as soon as its GNT

is removed The number of clocks programmed

into the MLT Register represents the guaranteed time slice (measured in PCICLKs) allotted to the PCEB after

which it surrenders the bus as soon as its GNT

is removed (Actual termination does not occur until the

target is ready) Each master on PCI contains a master latency timer The relative values programmed in each

master timer determines how much of the PCI bandwidth is available to that master Generally if the EISA bus

is heavily loaded with masters the PCEB MLT register would be programmed with a relatively large value to

give the PCEB a larger share of the PCI bus bandwidth

82375EB Datasheet(PDF) 82 Page - Intel Corporation

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