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82375EB Datasheet(PDF) 88 Page - Intel Corporation |
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82375EB Datasheet(HTML) 88 Page - Intel Corporation |
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88 / 131 page ![]() 82375EBSB Table 6 Fixed Priority Mode Bank Control Bits (Continued) Mode Bank Priority 3 2b 2a 1 0 Highest Lowest x 1 1 x x Reserved 10 1 0 0 0 0 PCEBREQ REQ0 REQ2 CPUREQ REQ3 REQ1 11 1 0 0 0 1 REQ0 PCEBREQ REQ2 CPUREQ REQ3 REQ1 12 1 0 0 1 0 PCEBREQ REQ0 REQ2 REQ3 CPUREQ REQ1 13 1 0 0 1 1 REQ0 PCEBREQ REQ2 REQ3 CPUREQ REQ1 14 1 0 1 0 0 CPUREQ REQ3 PCEBREQ REQ0 REQ2 REQ1 15 1 0 1 0 1 CPUREQ REQ3 REQ0 PCEBREQ REQ1 REQ2 16 1 0 1 1 0 REQ3 CPUREQ PCEBREQ REQ0 REQ2 REQ1 17 1 0 1 1 1 REQ3 CPUREQ REQ0 PCEBREQ REQ2 REQ1 18 1 1 0 0 0 REQ2 CPUREQ REQ3 PCEBREQ REQ0 REQ1 19 1 1 0 0 1 REQ2 CPUREQ REQ3 REQ0 PCEBREQ REQ1 1A 1 1 0 1 0 REQ2 REQ3 CPUREQ PCEBREQ REQ0 REQ1 1B 1 1 0 1 1 REQ2 REQ3 CPUREQ REQ0 PCEBREQ REQ1 x 1 1 x x Reserved Note that these two tables are permutations of the same table with different value of the Bank 3 fixed priority control bit The fixed bank control bit(s) selects which requester is the highest priority device within that particular bank Bits 74 must be programmed to all 0’s (rotate mode disabled) to get these combinations The selectable fixed priority schemes provide 24 of the 128 possible fixed mode permutations possible for the six masters 88 |
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