82375EB datasheet(50/131 Pages) INTEL

50 / 131 page

82375EBSB

2 Subtractive decoding For PCI memory or IO cycles the PCEB uses subtractive decoding (or negative

decoding described in

3 of this list for the 82375SB) to respond to addresses that are not positively

decoded With subtractive decoding if a memory or IO cycle is not claimed on the PCI Bus (via

DEVSEL ) the PCEB forwards the cycle to the EISA Bus The PCEB waits a programmable number of

PCICLKs (1 to 3 PCICLKs as selected via the PCICON Register) for a PCI agent to claim the cycle If the

cycle is not claimed within the programmed number of PCICLKs (DEVSEL

time-out) the PCEB claims the

cycle (asserts DEVSEL ) and forwards it to the EISA Bus Note that the number of PCICLKs for a

DEVSEL

time-out should be programmed to accommodate the slowest PCI Bus device

3 Negative decoding For the 82375SB negative decoding is a programmable option (via the PDCON

positively decoded by the PCEB as a main memory area (one of the MEMCS

generation areas) and is not

in one of the four programmable EISA-to-PCI memory regions (defined by MEMREGN 41 ) is immediately

forwarded to the EISA Bus This occurs without waiting for a DEVSEL

time-out to see if the cycle is going

to be claimed on the PCI Bus Thus negative decoding can reduce the latency incurred by waiting for a

DEVSEL

time-out that is associated with subtractive decoding This increases throughput to the EISA Bus

for unclaimed PCI memory cycles If the DEVSEL

time-out is set to a 2 PCICLKtime-out the latency is

reduced by 1 PCICLK and for a 3 PCICLK time-out the latency is reduced by 2 PCICLKs For more

information on negative (and subtractive) decoding see Section 4113 Subtractively and Negatively De-

coded Cycles to EISA

Note that negative decoding imposes a restriction on the PCI system memory address map PCI memory-

mapped devices are restricted to one of the four programmable EISA-to-PCI regions (MEMREGN 41 )

These regions always use subtractive decoding to forward an unclaimed cycle to the EISA Bus even if

negative decoding is enabled Locating devices in these regions ensures that the PCI device has the

allotted number of programmed PCICLKs (DEVSEL

time-out) to respond with DEVSEL

Further since

the PCEB does not negatively decode IO space addresses enabling this feature does not impose restric-

tions on devices that are mapped to PCI IO space

41 PCI Cycle Address Decoding

The PCEB decodes addresses presented on the multiplexed PCI addressdata bus during the address bus

phase AD 310 and the byte enables (CBE 30

during the data phase) are used for address decoding

CBE 30

are used during the data phase to indicate which byte lanes contain valid data For memory

cycles the PCI address decoding is always a function of AD 312

In the case of IO cycles all 32 address

bits (AD 310 ) are used to provide addressing with byte granularity For configuration cycles only a subset of

the address lines carry address information

The PCEB decodes the following PCI cycle addresses based on the contents of the relevant programmable

registers

1 Positively decodes PCEB configuration registers

2 Positively decodes IO addresses contained within the PCEB (BIOS Timer)

3 Positively decodes the following compatibility IO registers to improve performance a) Interrupt controller

(8259) IO registers contained within the ESC to optimize interrupt processing if enabled through the

PDCON Register b) IDE registers if enabled through the PDCON Register

4 Positively decodes four programmable memory address regions contained within the PCI memory space

82375EB Datasheet(PDF) 50 Page - Intel Corporation

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