82375EB datasheet(84/131 Pages) INTEL

84 / 131 page

82375EBSB

5311 Address Phase

As a master the PCEB drives AD 310 and CBE 30

and calculates the corresponding parity value and

drives it on the PAR signal 1 clock later As a target the PCEB does not check parity during the address

phase of a bus cycle

5312 Data Phase

As a master during a write cycle the PCEB drives AD 310 and CBE 30

and calculates the correspond-

ing parity value and drives it on the PAR signal 1 clock later

As a master during a read cycle the PCEB only drives CBE 30

The responding target drives AD 310

lines (data) and calculates parity based on the received CBE 30

and outgoing AD 310 signals The

target drives PAR during the following clock The PCEB calculates parity based on the outgoing CBE 30

and the incoming AD 310 signals at the end of the data phase It compares it with the incoming value of the

PAR signal and asserts PERR

if there is no match

As a target during a write cycle the PCEB calculates parity on the incoming AD 310 and CBE 30

signals

and compares the result on the next clock with the incoming value on the PAR signal If the value does not

match the PCEB asserts PERR

As a target during a read cycle the PCEB calculates parity on the incoming CBE 30

and outgoing

AD 310 signals The PCEB drives the calculated parity value during the next clock The master of the

transaction receives the data calculates parity on its outgoing CBE 30

and incoming AD 310 signals

and compares its calculated value on the next clock with the parity value on the PAR signal (supplied by the

PCEB) If the values do not match the master asserts PERR

532 PARITY ERRORPERR

SIGNAL

When the PCEB is involved in a bus transaction (master or target) it asserts the PERR

signal if enabled via

the PCICMD Register to indicate a parity error for the bus cycle PERR

is a sustained tri-state (sts) type of

signal (see Section 20 Signal Description) Note that PCI parity errors signaled by PERR

are reported to

the host processor via the ESC’s system interrupt control logic When the PCEB detects a parity error during

one of its bus transactions it sets the parity error status bit in the PCI Status Register regardless of whether

the PERR

signal is enabled via the PCICMD Register

533 SYSTEM ERRORS

The PCEB does not generate system errors (SERR ) Thus the PCEB does not have the capability of

indicating parity errors during the address phase in which it is a potential target (ie not a master) Note that

system errors are reported via the ESC (companion chip)

82375EB Datasheet(PDF) 84 Page - Intel Corporation

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