82375EB datasheet(92/131 Pages) INTEL

92 / 131 page

82375EBSB

5432 Master Retry Timer

For any other retried PCI cycle the arbiter masks the REQ

and flags it to be cleared by the expiration of a

programmable timer The first retry in this category triggers the programmable timer Subsequent retries in this

category are masked but do not reset the timer Expiration of this programmable timer unmasks all REQ s

that are masked for this reason The Retry Timer is programmable to 0 (disabled) 16 32 or 64 PCICLKs

If no other PCI masters are requesting the PCI Bus all of the REQ s masked for the timer are cleared and the

timer is set to 0 Note that when there is a pending request that is internally masked the PCEB does not park

the CPU on the PCI Bus (ie PCI agent that uses CPUREQ

CPUGNT

signal pair)

544 BUS LOCK MODE

As an option the PCEB arbiter can be configured to run in Bus Lock Mode or Resource Lock Mode (default)

The Bus Lock Mode is used to lock the entire PCI Bus This may improve performance in some systems that

frequently run quick read-modify-write cycles (ie access to the VGA frame buffer using the XCHG x86 instruc-

tion that automatically asserts the CPU LOCK

signal) Bus Lock Mode emulates the LOCK environment

found in today’s PC by restricting bus ownership when the PCI Bus is locked While Bus Lock Mode improves

performance in some systems it may cause performance problems in other systems With Bus Lock enabled

the arbiter recognizes a LOCK

being driven by an initiator and does not allow any other PCI initiator to be

granted the PCI Bus until LOCK

and FRAME

are both negated indicating the master released lock When

Bus Lock is disabled the default resource lock mechanism is implemented (normal resource lock) and a

higher priority PCI initiator could intervene between the cycles that are part of the locked sequence and run

non-exclusive accesses to any unlocked resource

CAUTION

Bus Lock mode should not be used with non-GAT mode If the system is initialized for both Bus Lock

mode and non-GAT mode a deadlock situation might occur in the case where the first access to the

locked device is a write instead of a read and the locked device has data in its internal posted write

buffer In GAT mode andor Resource Lock mode this condition can not happen If it is absolutely

necessary to operate the system in the above mentioned combination of modes then the posted

write buffers of the device that might be involved in locked operations (typically semaphore in main

memory) must be disabled

545 MEMREQ

FLSHREQ

AND MEMACK

PROTOCOL

Before an EISA master or DMA can be granted the PCI Bus it is necessary that all PCI system posted write

buffers be flushed Also since the EISA-originated cycle could access memory on the HostPCI Bridge it is

possible that the EISA master or DMA could be held in wait states (via EXRDY) waiting for the HostPCI

Bridge arbitration for longer than the 21 ms EISAISA specification The PCEB has an optional mode called

Guaranteed Access Time mode (GAT) that ensures that this timing specification is not violated This is accom-

plished by delaying the EISA grant signal to the requesting master or DMA until the EISA Bus PCI Bus and the

system memory bus are arbitrated for and owned

The three sideband signals MEMREQ

FLSHREQ

and MEMACK

are used to support the system Post-

ed Write Buffer flushing and Guaranteed Access Time mechanism The MEMACK

signal is the common

acknowledge signal for both mechanisms Note that when MEMREQ

is asserted FLSHREQ

is also

asserted Table 7 shows the relationship between MEMREQ

and FLSHREQ

82375EB Datasheet(PDF) 92 Page - Intel Corporation

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