82375EB datasheet(20/131 Pages) INTEL

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82375EBSB

24 EISA Interface Signals

Pin Name

Type

Description

BCLK

BUS CLOCK

BCLK is the system clock used to synchronize events on the EISA Bus

The ESC device generates BCLK (BCLKOUT) which is a divided down clock from a

PCICLK BCLK runs at a frequency that is dependent on PCICLK and a selected

division factor (within the ESC) For example a 25 MHz PCICLK and a division factor of

3 results in an 833 MHz BCLK

START

provides timing control at the start of the cycle and remains asserted

for one BCLK period

When the PCEB is an EISA master START

is an output signal START

is asserted

after LA 3124

LA 232 and MIO

become valid START

is negated on the

rising edge of the BCLK one BCLK after it was asserted The trailing edge of START

is always delayed from the rising edge of BCLK

When the PCEB is an EISA master for cycles to a mismatched slave (see note at the

end of this section) START

becomes an input signal at the end of the first START

phase and remains an input until the negation of the last CMD

The ESC gains the

control of the transfer and generates START

When the PCEB is an EISA slave START

is an input signal It is sampled on the rising

edge of BCLK

Upon PCIRST

this signal is tri-stated and placed in output mode

CMD

COMMAND

CMD

provides timing control within the cycle In all cases CMD

is an

input to the PCEB from the ESC CMD

is asserted from the rising edge of BCLK

simultaneously with the negation of START

and remains asserted until the end of the

cycle

MIO

MEMORY OR IO

MIO

identifies the current cycle as a memory or an IO cycle

MIO

is pipelined from one cycle to the next and must be latched by the slave

MIO

1 indicates a memory cycle and MIO

0 indicates an IO cycle

When the PCEB is an EISA master the MIO

is an output signal When the PCEB is

an EISA slave MIO

is an input signal The PCEB responds as an EISA slave for both

memory and IO cycles Upon PCIRST

this signal is tri-stated and is placed in output

mode

WRITE OR READ

identifies the cycle as a write or a read cycle The WR

signal is pipelined from one cycle to the next and must be latched by the slave WR

1 indicates a write cycle and WR

0 indicates a read cycle

When the PCEB is an EISA master WR

is an output signal When the PCEB is an

EISA slave WR

is an input signal Upon PCIRST

this signal is tri-stated and

placed in output mode

82375EB Datasheet(PDF) 20 Page - Intel Corporation

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