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82375EB Datasheet(PDF) 60 Page - Intel Corporation |
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82375EB Datasheet(HTML) 60 Page - Intel Corporation |
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60 / 131 page  82375EBSB 290477 – 48 NOTES 1 The four programmable EISA-to-PCI regions (Regions 41 ) are not shown These regions can be located anywhere within the 4 GByte memory space Accesses to these regions are forwarded to the PCI Bus 2 EISA cycles that access shaded regions are contained to the EISA Bus unless the access hits one of the four programmable EISA-to-PCI regions described in note 1 3 Memory accesses to non-shaded areas are forwarded to the PCI Bus if the regions is enabled If the region is disabled the access is contained to the EISA Bus unless the access hits one of the four programmable EISA-to-PCI regions described in note 1 Figure 6 EISA Address Decoder Map EISA memory cycles positively decoded for forwarding to PCI are allowed to be handled by the PCEB’s Line Buffer management logic if the line buffering is enabled through the PCICON Register 60 |
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