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82375EB Datasheet(PDF) 100 Page - Intel Corporation |
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82375EB Datasheet(HTML) 100 Page - Intel Corporation |
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100 / 131 page  82375EBSB The Line Buffer control logic dynamically switches between two prefetch modesHalf Line Prefetch (16 bytes fetch) and Full Line Prefetch (32 bytes fetch) The prefetch control logic has implemented a Sequential Access Flag which is cleared before the initial prefetch Initial prefetch (first data fetch) starts in the Half Line Prefetch mode and is extended to Full Line Prefetch mode immediately after MSBURST is sampled asserted at which time the Sequential Access Flag is automatically set (this is done on-the-fly during the first line fetch) If after the initial prefetch the Sequential Access Flag has not been set (MSBURST remained not asserted) and the control logic recognizes two consecutive hits (in incrementally sequential Dwords including the first one which is originally requested) the Sequential Access Flag is set and the prefetch control logic switches to Full Line Prefetch mode An additional 32-byte line (or fraction depending on alignment) will be fetched When the Sequential Access Flag is set prefetching is accomplished using the Full Line Prefetch mode Each time a line buffer (32 bytes) is available an additional line will be fetched as long as the Sequential Access Flag remains set When out-of-order access is recognized within the prefetched data or a miss occurs when there is valid fetched data the Sequential Access Flag is cleared and the prefetch mode changes to Half Line Prefetch Also the Sequential Access Flag is cleared when MSBURST transitions from active to inactive When the Sequential Access Flag is not asserted the prefetch control logic operates in Half Line Prefetch mode during which only 16 bytes of data is fetched at a time The same test for sequential access is repeated and if access is recognized the Sequential Access Flag is set and the control switches to Full Line Prefetch mode 62 Buffer Management Summary Table 8 shows Line Buffer for different cycles Note that the first three columns together define the cycles that may trigger buffer activity Table 8 Buffer Management Summary Master Cycle Type Slave Line Buffer Data Line Buffer Data (Origin) (Destination) in Write State in Read State PCI Memory Read EISA Flush No Action PCI Memory Write EISA No Action Invalidate PCI IO Read EISA Flush No Action PCI IO Write EISA No Action Invalidate PCI Interrupt Acknowledge PCEBESC Flush No Action PCI Configuration Cycle PCEB Registers No Action No Action PCI Memory ReadWrite PCI No Action No Action PCI IO ReadWrite PCI No Action No Action EISA Bus Ownership Change Flush No Action EISA Memory ReadWrite EISA No Action No Action 100 |
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