82375EB datasheet(102/131 Pages) INTEL

102 / 131 page

82375EBSB

5 The PCEB contains EISA data swap buffers for data size translations between mismatched PCI Bus

and EISA Bus transfers and between mismatched devices contained on the EISA Bus Thus if data

size translation is needed the PCEB is involved in cycles contained to the EISA Bus even if the

PCEB is neither the master or slave For data size translation operations see Section 80 EISA Data

Swap Buffers

6 For ISA master cycles to PCI memory or IO the ESC translates the ISA signals to EISA signals The

PCEB as an EISA slave forwards the cycle to the PCI Bus

7 For ISA master cycles to ISAEISA slaves the PCEB is not involved except when the cycle requires

data size translations See the ESC data sheet for cycles that are contained within the EISA Bus (ie

EISA-to-EISA EISA-to-ISA ISA-to-ISA and ISA-to-EISA device cycles)

8 In this section LA 3124

and LA 232 are collectively referred to as LA 312

71 PCEB As An EISA Master

The PCEB is an EISA master for PCI-initiated cycles targeted to the EISA Bus When the PCEB decodes the

PCI cycle as a cycle destined to the EISA Bus (via subtractive or negative (82374SB only) decoding as

described in Section 40 Address Decoding) the PCEB becomes a slave on the PCI Bus If the PCEB owns

the EISA Bus the cycle is forwarded to the EISAISA device If the PCEB does not own the EISA Bus

(EISAHOLDA is asserted to the ESC) the PCI master is retried and the PCEB issues an EISA Bus request to

the ESC For PCI-to-EISA IO and memory readwrite accesses the PCEB runs standard EISA Bus cycles

When cycles are forwarded to a matched EISAISA slave the PCEB is the EISA master and controls the

transfer until the cycle is terminated For mismatched cycles to an EISAISA slave the PCEB backs off the

EISA Bus as described in Section 713 Back-Off Cycle

711 STANDARD EISA MEMORY AND IO READWRITE CYCLES

The standard EISA cycle completes one transfer each two BCLK periods (zero wait states) The standard

EISA memory or IO cycle begins when the PCEB presents a valid address on LA 312 and drives MIO

high for a memory cycle and low for an IO cycle The address can become valid at the end of the previous

cycle to allow address pipelining The EISA slave decodes the address and asserts the appropriate signals to

indicate the type of slave and whether it can perform any special timings The slave asserts EX32

or EX16

to indicate support of EISA cycles

For extended cycles the EISA slave introduces wait states using the EXRDY signal Wait states allow a slower

slave to get ready to complete the transfer The slave negates EXRDY after it decodes a valid address and

samples START

asserted The slave may hold EXRDY negated for a maximum of 25 ms to complete a

transfer and must release EXRDY synchronous to the falling edge of BCLK to allow a cycle to complete Note

that the PCEB as an EISA master never introduces wait states

Figure 25 shows three data transfer cycles between an EISA master and an EISA slave The first transfer is an

extended transfer (EXRDY negated) followed by two standard cycles For PCI cycles that are forwarded to the

EISA Bus the PCEB is the EISA master The PCEB asserts START

to indicate the start of a cycle The

PCEB also drives WR

to indicate a read or write cycle and BE 30

to indicate the active bytes The

LA 312 and the BE 30 remain valid until after the negation of START

A slave that needs to latch the

address does so on the trailing edge of START

The ESC asserts CMD

simultaneously with the negation of START

to control data transfer to or from the

slave If a read cycle is being performed the slave presents the requested data when CMD

is asserted and

holds it valid until CMD

is negated by the ESC For a write cycle the PCEB presents the data prior to the

assertion of CMD

and the slave latches it on or before the trailing edge of CMD

102

82375EB Datasheet(PDF) 102 Page - Intel Corporation

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