AM3874 datasheet(285/361 Pages) TI

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AM3874, AM3871

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SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

8.13.4.1.1.7 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass capacitors, MPU/DDR power, and

MPU/DDR ground connections. Table 8-59 contains the specification for the HS bypass capacitors as well

as for the power connections on the PCB.

Table 8-59. High-Speed Bypass Capacitors

NO.

PARAMETER

MIN

MAX

UNIT

HS bypass capacitor package size(1)

0402

10 Mils

Distance from HS bypass capacitor to device being bypassed

250

Mils

Number of connection vias for each HS bypass capacitor(2)

Vias

Trace length from bypass capacitor contact to connection via

Mils

Number of connection vias for each MPU power/ground ball

Vias

Trace length from MPU power/ground ball to connection via

Mils

Number of connection vias for each DDR2 device power/ground ball

Vias

Trace length from DDR2 device power/ground ball to connection via

Mils

DVDD18 HS bypass capacitor count(3)(4)

Devices

DVDD18 HS bypass capacitor total capacitance(5)

2.4

μF

DDR device HS bypass capacitor count(6)(7)

Devices

DDR device HS bypass capacitor total capacitance(7)

0.4

μF

(1)

LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.

(2)

An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

(3)

These devices should be placed as close as possible to the device being bypassed.

(4)

Use half of these capacitors for DDR[0] and half for DDR[1].

(5)

Use half of these capacitors for DDR[0] and half for DDR[1].

(6)

These devices should be placed as close as possible to the device being bypassed.

(7)

Per DDR device.

8.13.4.1.1.8 Net Classes

Table 8-60 lists the clock net classes for the DDR2 interface. Table 8-61 lists the signal net classes, and

associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the

termination and routing rules that follow.

Table 8-60. Clock Net Class Definitions

CLOCK NET CLASS

MPU PIN NAMES

DDR[x]_CLK/DDR[x]_CLK

DQS0

DDR[x]_DQS[0]/DDR[x]_DQS[0]

DQS1

DDR[x]_DQS[1]/DDR[x]_DQS[1]

DQS2(1)

DDR[x]_DQS[2]/DDR[x]_DQS[2]

DQS3(1)

DDR[x]_DQS[3]/DDR[x]_DQS[3]

(1)

Only used on 32-bit wide DDR2 memory systems.

Peripheral Information and Timings

285

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