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AD9680

Data Sheet

Rev. C | Page 38 of 97

ANALOG INPUT FREQUENCY (MHz)

1513.4

1607.4

1701.5

1795.6

1889.8

4.5×

5.5×

6.5×

7.5×

8.5×

Figure 123. Buffer Current Sweeps, AD9680-1000 (SFDR vs. IBUFF);

1500 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 115

In certain high frequency applications, the SFDR can be improved

by reducing the full-scale setting, as shown in Table 10. At high

frequencies, the performance of the ADC core is limited by jitter.

The SFDR can be improved by backing off of the full scale level.

Figure 124 shows the SFDR and SNR vs. full-scale input level at

different high frequencies for the AD9680-1000.

1.52GHz

1.65GHz

1.76GHz

1.9GHz

1.95GHz

–3

–2

–1

INPUT LEVEL (dBFS)

1.52GHz

1.65GHz

1.76GHz

1.9GHz

1.95GHz

Figure 124. SNR/SFDR vs. Analog Input Level vs. Input Frequencies, AD9680-1000

Figure 125, Figure 126, and Figure 127 show the SFDR vs.

analog input frequency for various buffer settings for the

AD9680-820. The recommended settings shown in Table 10

were used to take the data while changing the contents of

ANALOG INPUT FREQUENCY (MHz)

1.5×

2.0×

3.0×

4.5×

Figure 125. Buffer Current Sweeps, AD9680-820 (SFDR vs. IBUFF);

fIN < 500 MHz; Front-End Network Shown in Figure 115

ANALOG INPUT FREQUENCY (MHz)

3.5×

4.5×

5.5×

6.5×

7.5×

Figure 126. Buffer Current Sweeps, AD9680-820 (SFDR vs. IBUFF);

500 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 115

ANALOG INPUT FREQUENCY (MHz)

6.5×

7.5×

8.5×

Figure 127. Buffer Current Sweeps, AD9680-820 (SFDR vs. IBUFF);

1000 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 115

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