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Data Sheet

AD9680

Rev. C | Page 73 of 97

JESD204B supported output configurations (see Table 26):

•

N΄ = 16 bits

•

N = 14 bits

•

L = 1, M = 8, and F = 16, or L = 2, M = 8, and F = 8 (quick

configuration = 0x1C or 0x5B)

•

CS = 0 to 1

•

K = 32

•

Output serial line rate = 10 Gbps per lane (L = 1) or 5 Gbps

per lane (L = 2)

For L = 1, low line rate mode is disabled. For L = 2, low line

rate mode is enabled.

Example 2 shows the flexibility in the digital and lane

configurations for the AD9680. The sample rate is 1 GSPS;

however, the outputs are all combined in either one or two

lanes, depending on the I/O speed capability of the receiving

device.

DDC 0

CONVERTER 0

CONVERTER 1

REAL/I

DDC 1

CONVERTER 2

CONVERTER 3

REAL/Q

DDC 2

CONVERTER 4

CONVERTER 5

REAL/I

DDC 3

CONVERTER 6

CONVERTER 7

REAL/Q

I/Q

CROSSBAR

MUX

ADC A

SAMPLING

REAL

ADC B

SAMPLING

REAL

SYNCHRONIZATION

CONTROL CIRCUITS

SYSREF

L JESD204B

LANES UP TO

12.5Gbps

JESD204B

LANES

AT UP TO

12.5Gbps

Figure 170. Two ADC Plus Four DDC Mode

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