AD9680 datasheet(69/97 Pages) AD

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AD9680

Rev. C | Page 69 of 97

JESD204B TX CONVERTER MAPPING

To support the different chip operating modes, the AD9680

design treats each sample stream (real or I/Q) as originating

from separate virtual converters. The I/Q samples are always

mapped in pairs with the I samples mapped to the first virtual

converter and the Q samples mapped to the second virtual

converter. With this transport layer mapping, the number of

virtual converters are the same whether



A single real converter is used along with a digital

downconverter block producing I/Q outputs, or



An analog downconversion is used with two real

converters producing I/Q outputs.

Figure 167 shows a block diagram of the two scenarios

described for I/Q transport layer mapping.

The JESD204B Tx block for AD9680 supports up to four DDC

blocks. Each DDC block outputs either two sample streams (I/Q)

for the complex data components (real + imaginary), or one

sample stream for real (I) data. The JESD204B interface can be

configured to use up to eight virtual converters depending on the

DDC configuration. Figure 168 shows the virtual converters and

their relationship to the DDC outputs when complex outputs

are used. Table 25 shows the virtual converter mapping for each

chip operating mode when channel swapping is disabled.

REAL

CONVERTER 0

CONVERTER 1

ADC

90°

PHASE

JESD204B

L LANES

I/Q ANALOG MIXING

M = 2

ADC

REAL

CONVERTER 0

CONVERTER 1

JESD204B

L LANES

DIGITAL DOWNCONVERSION

M = 2

DIGITAL

DOWN

CONVERSION

Figure 167. I/Q Transport Layer Mapping

DDC 0

REAL/I

CONVERTER 0

CONVERTER 1

REAL/I

REAL/Q

DDC 1

REAL/I

CONVERTER 2

CONVERTER 3

REAL/I

REAL/Q

DDC 2

REAL/I

CONVERTER 4

CONVERTER 5

REAL/I

REAL/Q

DDC 3

REAL/I

CONVERTER 6

CONVERTER 7

REAL/I

REAL/Q

OUTPUT

INTERFACE

I/Q

CROSSBAR

MUX

ADC A

SAMPLING

REAL/I

ADC B

SAMPLING

REAL/Q

Figure 168. DDCs and Virtual Converter Mapping

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