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AD9680 Datasheet(PDF) 79 Page - Analog Devices |
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AD9680 Datasheet(HTML) 79 Page - Analog Devices |
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79 / 97 page  Product Overview Online Documentation Design Resources Discussion Sample & Buy Data Sheet AD9680 Rev. C | Page 79 of 97 JESD204B BLOCK TEST MODES In addition to the ADC pipeline test modes, the AD9680 also has flexible test modes in the JESD204B block. These test modes are listed in Register 0x573 and Register 0x574. These test patterns can be injected at various points along the output data path. These test injection points are shown in Figure 156. Table 30 describes the various test modes available in the JESD204B block. For the AD9680, a transition from test modes (Register 0x573 ≠ 0x00) to normal mode (Register 0x573 = 0x00) requires an SPI soft reset. This is done by writing 0x81 to Register 0x00 (self cleared). Transport Layer Sample Test Mode The transport layer samples are implemented in the AD9680 as defined by Section 5.1.6.3 in the JEDEC JESD204B Specification. These tests are shown in Register 0x571[5]. The test pattern is equivalent to the raw samples from the ADC. Interface Test Modes The interface test modes are described in Register 0x573, Bits[3:0]. These test modes are also explained in Table 30. The interface tests can be injected at various points along the data. See Figure 156 for more information on the test injection points. Register 0x573, Bits[5:4] show where these tests are injected. Table 31, Table 32, and Table 33 show examples of some of the test modes when injected at the JESD sample input, PHY 10-bit input, and scrambler 8-bit input. UP in the tables represent the user pattern control bits from the customer register map. Table 30. JESD204B Interface Test Modes Output Test Mode Bit Sequence Pattern Name Expression Default 0000 Off (default) Not applicable Not applicable 0001 Alternating checker board 0x5555, 0xAAAA, 0x5555, … Not applicable 0010 1/0 word toggle 0x0000, 0xFFFF, 0x0000, … Not applicable 0011 31-bit PN sequence X31 + X28 + 1 0x0003AFFF 0100 23-bit PN sequence X23 + X18 + 1 0x003AFF 0101 15-bit PN sequence X15 + X14 + 1 0x03AF 0110 9-bit PN sequence X9 + X5 + 1 0x092 0111 7-bit PN sequence X7 + X6 + 1 0x07 1000 Ramp output (X) % 216 Ramp size depends on test injection point 1110 Continuous/repeat user test Register 0x551 to Register 0x558 User Pattern 1 to User Pattern 4, then repeat 1111 Single user test Register 0x551 to Register 0x558 User Pattern 1 to User Pattern 4, then zeros Table 31. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x573[5:4] = 'b00) Frame Number Converter Number Sample Number Alternating Checkerboard 1/0 Word Toggle Ramp PN9 PN23 User Repeat User Single 0 0 0 0x5555 0x0000 (X) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 0 0 1 0x5555 0x0000 (X) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 0 1 0 0x5555 0x0000 (X) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 0 1 1 0x5555 0x0000 (X) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 1 0 0 0xAAAA 0xFFFF (X +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 1 0 1 0xAAAA 0xFFFF (X +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 1 1 0 0xAAAA 0xFFFF (X +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 1 1 1 0xAAAA 0xFFFF (X +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 2 0 0 0x5555 0x0000 (X +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 2 0 1 0x5555 0x0000 (X +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 2 1 0 0x5555 0x0000 (X +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 2 1 1 0x5555 0x0000 (X +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 3 0 0 0xAAAA 0xFFFF (X +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] 3 0 1 0xAAAA 0xFFFF (X +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] 3 1 0 0xAAAA 0xFFFF (X +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] 3 1 1 0xAAAA 0xFFFF (X +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] 4 0 0 0x5555 0x0000 (X +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000 4 0 1 0x5555 0x0000 (X +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000 4 1 0 0x5555 0x0000 (X +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000 4 1 1 0x5555 0x0000 (X +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000 |
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