AD9680 datasheet(85/97 Pages) AD

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Data Sheet

AD9680

Rev. C | Page 85 of 97

Reg

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

ADC Function Registers

0x024

V_1P0

control

1.0 V

reference

select

0 =

internal

1 =

external

0x00

0x028

Temperature

diode

Diode

selection

0 =

no diode

selected

1 =

temper-

ature

diode

selected

0x00

Used in

conjunc-

tion with

Reg.

0x040

0x03F

PDWN/

STBY pin

control (local)

0 = PDWN/

STBY

enabled

1 =

disabled

0x00

Used in

conjunc-

tion with

Reg.

0x040

Chip pin

control

PDWN/STBY function

00 = power down

01 = standby

10 = disabled

Fast Detect B (FD_B)

000 = Fast Detect B output

001 = JESD204B LMFC output

010 = JESD204B internal SYNC~ output

111 = disabled

Fast Detect A (FD_A)

000 = Fast Detect A output

001 = JESD204B LMFC output

010 = JESD204B internal SYNC~ output

011 = temperature diode

111 = disabled

0x3F

0x10B

Clock divider

000 = divide by 1

001 = divide by 2

011 = divide by 4

111 = divide by 8

0x00

0x10C

Clock divider

phase (local)

Independently controls Channel A and Channel B clock

divider phase offset

0000 = 0 input clock cycles delayed

0001 = ½ input clock cycles delayed

0010 = 1 input clock cycles delayed

0011 = 1½ input clock cycles delayed

0100 = 2 input clock cycles delayed

0101 = 2½ input clock cycles delayed

…

1111 = 7½ input clock cycles delayed

0x00

0x10D

Clock divider

and SYSREF

control

Clock

divider

auto phase

adjust

0 =

disabled

1 =

enabled

Clock divider negative

skew window

00 = no negative skew

01 = 1 device clock of

negative skew

10 = 2 device clocks of

negative skew

11 = 3 device clocks of

negative skew

Clock divider positive

skew window

00 = no positive skew

01 = 1 device clock of

positive skew

10 = 2 device clocks of

positive skew

11 = 3 device clocks of

positive skew

0x00

Clock

divider

must be

0x117

Clock delay

control

Clock fine

delay

adjust

enable

0 =

disabled

1 =

enabled

0x00

Enabling

the clock

fine delay

adjust

causes a

datapath

reset

AD9680 Datasheet(PDF) 85 Page - Analog Devices

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