AD9680 datasheet(74/97 Pages) AD

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AD9680

Data Sheet

Rev. C | Page 74 of 97

MULTICHIP SYNCHRONIZATION

The AD9680 has a SYSREF± input that provides flexible options

for synchronizing the internal blocks. The SYSREF± input is a

source synchronous system reference signal that enables multichip

synchronization. The input clock divider, DDCs, signal monitor

block, and JESD204B link can be synchronized using the SYSREF±

input. For the highest level of timing accuracy, SYSREF± must

meet setup and hold requirements relative to the CLK± input.

The flowchart in Figure 171 describes the internal mechanism

for multichip synchronization in the AD9680. The AD9680

supports several features that aid users in meeting the

requirements set out for capturing a SYSREF± signal. The

SYSREF sample event can be defined as either a synchronous

low to high transition, or a synchronous high to low transition.

Additionally, the AD9680 allows the SYSREF signal to be sampled

using either the rising edge or falling edge of the CLK± input.

The AD9680 also has the ability to ignore a programmable

number (up to 16) of SYSREF± events. The SYSREF± control

options can be selected using Register 0x120 and Register 0x121.

AD9680 Datasheet(PDF) 74 Page - Analog Devices