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AD9680

Data Sheet

Rev. C | Page 76 of 97

SYSREF± SETUP/HOLD WINDOW MONITOR

To ensure a valid SYSREF signal capture, the AD9680 has a

SYSREF± setup/hold window monitor. This feature allows the

system designer to determine the location of the SYSREF± signals

relative to the CLK± signals by reading back the amount of

setup/hold margin on the interface through the memory map.

Figure 172 and Figure 173 show the setup and hold status values

for different phases of SYSREF±. The setup detector returns the

status of the SYSREF± signal before the CLK± edge, and the

hold detector returns the status of the SYSREF signal after the

CLK± edge. Register 0x128 stores the status of SYSREF± and

lets the user know if the SYSREF± signal is captured by the ADC.

VALID

REG 0x128[3:0]

CLK±

INPUT

SYSREF±

INPUT

FLIP-FLOP

HOLD (MIN)

FLIP-FLOP

HOLD (MIN)

FLIP-FLOP

SETUP (MIN)

0xF

0xE

0xD

0xC

0xB

0xA

0x9

0x8

0x7

0x6

0x5

0x4

0x3

0x2

0x1

0x0

Figure 172. SYSREF± Setup Detector

AD9680 Datasheet(PDF) 76 Page - Analog Devices

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