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AD9680 Datasheet(PDF) 49 Page - Analog Devices

Part # AD9680
Description  Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter
PDF  97 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9680 Datasheet(HTML) 49 Page - Analog Devices

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Product
Overview
Online
Documentation
Design
Resources
Discussion
Sample
& Buy
Data Sheet
AD9680
Rev. C | Page 49 of 97
NCO
+
MIXER
(OPTIONAL)
DDC 3
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 6
Q CONVERTER 7
I
Q
NCO
+
MIXER
(OPTIONAL)
DDC 0
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 0
Q CONVERTER 1
I
Q
NCO
+
MIXER
(OPTIONAL)
DDC 1
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 2
Q CONVERTER 3
I
Q
NCO
+
MIXER
(OPTIONAL)
DDC 2
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 4
Q CONVERTER 5
I
Q
ADC
SAMPLING
AT
fS
REAL/I
ADC
SAMPLING
AT
fS
REAL/I
SYNCHRONIZATION
CONTROL CIRCUITS
SYSREF
Figure 146. DDC Detailed Block Diagram
Figure 147 shows an example usage of one of the four DDC
blocks with a real input signal and four half-band filters (HB4,
HB3, HB2, and HB1). It shows both complex (decimate by 16)
and real (decimate by 8) output options.
When DDCs have different decimation ratios, the chip
decimation ratio (Register 0x201) must be set to the lowest
decimation ratio of all the DDC blocks. In this scenario,
samples of higher decimation ratio DDCs are repeated to match
the chip decimation ratio sample rate. Whenever the NCO
frequency is set or changed, the DDC soft reset must be issued.
If the DDC soft reset is not issued, the output may potentially
show amplitude variations.
Table 11, Table 12, Table 13, Table 14, and Table 15 show the
DDC samples when the chip decimation ratio is set to 1, 2, 4, 8,
or 16, respectively.



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