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AD9680

Data Sheet

Rev. C | Page 56 of 97

For example, if the ADC sampling frequency (fS) is 1250 MSPS

and the carrier frequency (fC) is 416.667 MHz,

MHz

1365

1250

667

416

(













Mod

round

FTW

NCO

This, in turn, converts to 0x555 in the 12-bit twos complement

representation for NCO_FTW. The actual carrier frequency can

be calculated based on the following equation:

MHz

416

−

FTW

NCO

actual

A 12-bit POW is available for each NCO to create a known phase

relationship between multiple AD9680 chips or individual DDC

channels inside one AD9680.

The following procedure must be followed to update the FTW

and/or POW registers to ensure proper operation of the NCO:

•

Write to the FTW registers for all the DDCs.

•

Write to the POW registers for all the DDCs.

•

Synchronize the NCOs either through the DDC soft reset

bit accessible through the SPI, or through the assertion of

the SYSREF± pin.

Note that the NCOs must be synchronized either through SPI

or through the SYSREF± pin after all writes to the FTW or POW

registers have completed. This synchronization is necessary to

ensure the proper operation of the NCO.

NCO Synchronization

Each NCO contains a separate phase accumulator word (PAW)

that determines the instantaneous phase of the NCO. The initial

reset value of each PAW is determined by the POW described

in the Setting Up the NCO FTW and POW section. The phase

increment value of each PAW is determined by the FTW.

Two methods can be used to synchronize multiple PAWs within

the chip:

•

Using the SPI. The DDC NCO soft reset bit in the DDC

synchronization control register (Register 0x300, Bit 4)

can be used to reset all the PAWs in the chip. This is

accomplished by toggling the DDC NCO soft reset bit.

This method can only be used to synchronize DDC

channels within the same AD9680 chip.

•

Using the SYSREF± pin. When the SYSREF± pin is enabled

in the SYSREF± control registers (Register 0x120 and

in Bits[1:0] in the DDC synchronization control register

(Register 0x300), any subsequent SYSREF± event resets all

the PAWs in the chip. This method can be used to synchronize

DDC channels within the same AD9680 chip, or DDC

channels within separate AD9680 chips.

Mixer

The NCO is accompanied by a mixer, whose operation is

similar to an analog quadrature mixer. The mixer performs the

downconversion of input signals (real or complex) by using the

NCO frequency as a local oscillator. For real input signals, this

mixer performs a real mixer operation (with two multipliers).

For complex input signals, the mixer performs a complex mixer

operation (with four multipliers and two adders). The mixer

adjusts its operation based on the input signal (real or complex)

provided to each individual channel. The selection of real or

complex inputs can be controlled individually for each DDC

block by using Bit 7 of the DDC control register (Register 0x310,

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