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AD9680

Data Sheet

Rev. C | Page 78 of 97

TEST MODES

ADC TEST MODES

The AD9680 has various test options that aid in the system level

implementation. The AD9680 has ADC test modes that are

available in Register 0x550. These test modes are described in

Table 29. When an output test mode is enabled, the analog section

of the ADC is disconnected from the digital back-end blocks,

and the test pattern is run through the output formatting block.

Some of the test patterns are subject to output formatting, and

some are not. The PN generators from the PN sequence tests

can be reset by setting Bit 4 or Bit 5 of Register 0x550. These

tests can be performed with or without an analog signal (if

present, the analog signal is ignored); however, they do require

an encode clock.

If the application mode is set to select a DDC mode of

operation, the test modes must be enabled for each DDC

enabled. The test patterns can be enabled via Bit 2 and Bit 0 of

on which DDC(s) are selected. The (I) data uses the test

patterns selected for Channel A, and the (Q) data uses the test

patterns selected for Channel B. For DDC3 only, the (I) data

uses the test patterns from Channel A, and the (Q) data does

not output test patterns. Bit 0 of Register 0x387 selects the

Channel A test patterns to be used for the (I) data. For more

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

Table 29. ADC Test Modes1

Output Test Mode

Bit Sequence

Pattern Name

Expression

Default/

Seed Value

Sample (N, N + 1, N + 2, …)

0000

Off (default)

N/A

0001

Midscale short

00 0000 0000 0000

N/A

0010

+Full-scale short

01 1111 1111 1111

N/A

0011

−Full-scale short

10 0000 0000 0000

N/A

0100

Checkerboard

10 1010 1010 1010

N/A

0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555

0101

PN sequence long

X23 + X18 + 1

0x3AFF

0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6

0110

PN sequence short

X9 + X5 + 1

0x0092

0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697

0111

One-/zero-word toggle

11 1111 1111 1111

N/A

0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000

1000

User input

N/A

User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2],

User Pattern 1[15:2] … for repeat mode

User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2],

0x0000 … for single mode

1111

Ramp Output

(X) % 214

N/A

(X) % 214, (X +1) % 214, (X +2) % 214, (X +3) % 214

N/A means not applicable.

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