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WM5102 Datasheet(PDF) 34 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 34 Page - Wolfson Microelectronics plc |
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34 / 334 page  WM5102 Production Data w PD, June 2014, Rev 4.2 34 DIGITAL AUDIO INTERFACE - MASTER MODE Figure 6 Audio Interface Timing - Master Mode Note that BCLK and LRCLK outputs can be inverted if required; Figure 6 shows the default, non- inverted polarity. Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode AIFnBCLK cycle time tBCY 80 ns AIFn[TX/RX]LRCLK propagation delay from BCLK falling edge tLRD 0 12 ns AIFnTXDAT propagation delay from BCLK falling edge tDD 0 12 ns AIFnRXDAT setup time to BCLK rising edge tDSU 7 ns AIFnRXDAT hold time from BCLK rising edge tDH 5 ns Note: The descriptions above assume non-inverted polarity of AIFnBCLK and AIFn[TX/RX]LRCLK. |
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