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WM5102 Datasheet(PDF) 25 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 25 Page - Wolfson Microelectronics plc |
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25 / 334 page ![]() Production Data WM5102 w PD, June 2014, Rev 4.2 25 Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT MICVDD Charge Pump and Regulator (CP2 and LDO2) Output voltage VMICVDD 1.7 2.7 3.3 V Programmable output voltage step size 50 mV Maximum output current 8 mA Start-up time 4.7µF on MICVDD, IMICBIASn = 1mA 4.5 ms Frequency Locked Loop (FLL1, FLL2) Output frequency Normal operation, input reference supplied 13 52 MHz Free-running mode, no reference supplied 30 Lock Time FREF = 32kHz, FOUT = 24.576MHz 10 ms FREF = 12MHz, FOUT = 24.576MHz 1 RESET pin Input RESET input pulse width (To trigger a Hardware Reset, the RESET input must be asserted for longer than this duration) 1 µs Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. Device Reset Thresholds AVDD Reset Threshold VAVDD 0.54 0.96 V DCVDD Reset Threshold VDCVDD 0.59 0.81 V DBVDD1 Reset Threshold VDBVDD1 0.54 0.96 V Note that the reset thresholds are derived from simulations only, across all operational and process corners. Device performance is not assured outside the voltage ranges defined in the “Recommended Operating Conditions” section. Refer to this section for the WM5102 power-up sequencing requirements. |
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