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WM5102 Datasheet(PDF) 38 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 38 Page - Wolfson Microelectronics plc |
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38 / 334 page  WM5102 Production Data w PD, June 2014, Rev 4.2 38 4-WIRE (SPI) CONTROL MODE Figure 10 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle) Figure 11 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle) Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT SS ¯¯ falling edge to SCLK rising edge tSSU 2.6 ns SCLK falling edge to SS ¯¯ rising edge tSHO 0 ns SCLK pulse cycle time SYSCLK disabled (SYSCLK_ENA=0) tSCY 38.4 ns SYSCLK_ENA=1 and SYSCLK_FREQ = 000 76.8 SYSCLK_ENA=1 and SYSCLK_FREQ > 000 38.4 SCLK pulse width low tSCL 15.3 ns SCLK pulse width high tSCH 15.3 ns MOSI to SCLK set-up time tDSU 1.3 ns MOSI to SCLK hold time tDHO 1.7 ns SCLK falling edge to MISO transition tDL 0 7.8 ns |
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