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WM5102 Datasheet(PDF) 10 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 10 Page - Wolfson Microelectronics plc |
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10 / 334 page ![]() WM5102 Production Data w PD, June 2014, Rev 4.2 10 PIN NO NAME TYPE DESCRIPTION F11 LDOENA Digital Input Enable pin for LDO1 D13 LDOVDD Supply Supply for LDO1 E12 LDOVOUT Analogue Output LDO1 output H13 MCLK1 Digital Input Master clock 1 F12 MCLK2 Digital Input Master clock 2 C12 MICBIAS1 Analogue Output Microphone bias 1 D12 MICBIAS2 Analogue Output Microphone bias 2 C13 MICBIAS3 Analogue Output Microphone bias 3 B13 MICDET1/ HPOUT1FB2 Analogue Input Microphone & accessory sense input 1/ HPOUT1L and HPOUT1R ground feedback pin 2 E11, F1 MICVDD Analogue Output LDO2 output decoupling pin (generated internally by WM5102). (Can also be used as reference/supply for external microphones.) E13 RESET ¯¯¯¯¯¯ Digital Input Digital Reset input (active low) H12 SLIMCLK Digital Input / Output SLIMbus Clock input / output H11 SLIMDAT Digital Input / Output SLIMbus Data input / output L10 SPKCLK Digital Output Digital speaker (PDM) clock output K8 SPKDAT Digital Output Digital speaker (PDM) data output J1, J2 SPKGNDL Supply Left speaker driver ground (Return path for SPKVDDL) K1, K2 SPKGNDR Supply Right speaker driver ground (Return path for SPKVDDR) H2 SPKOUTLN Analogue Output Left speaker negative output H1 SPKOUTLP Analogue Output Left speaker positive output L2 SPKOUTRN Analogue Output Right speaker negative output L1 SPKOUTRP Analogue Output Right speaker positive output G1, G2 SPKVDDL Supply Left speaker driver supply M1, M2 SPKVDDR Supply Right speaker driver supply L9 TCK Digital Input JTAG clock input. Internal pull-down holds this pin at logic 0 for normal operation. M11 TDI Digital Input JTAG data input. Internal pull-down holds this pin at logic 0 for normal operation. K6 TDO Digital Output JTAG data output K7 TMS Digital Input JTAG mode select input. Internal pull-down holds this pin at logic 0 for normal operation. M12 TRST Digital Input JTAG Test Access Port reset (active low). Internal pull-down holds this pin at logic 0 for normal operation. D11 VREFC Analogue Output Bandgap reference decoupling capacitor connection |
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