WM5102 datasheet(87/334 Pages) WOLFSON

87 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

The WM5102 performs automatic checks to confirm that the SYSCLK frequency is high enough to

support the commanded DSP mixing functions. If an attempt is made to enable a DSP mixer path, and

there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that

any signal paths that are already active will not be affected under these circumstances.)

The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See

“General Purpose Input / Output” and “Interrupts” for further details.

The status bits in Registers R1600 to R2920 indicate the status of each of the digital mixers. If an

Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been

successfully enabled.

The WM5102 supports two DSP Status flags as outputs from the DSP. These are configurable within

the DSP to provide external indication of the required function(s). The DSP Status flags can be read

using the DSP_IRQn_STS registers described in Table 96 (see “Interrupts”).

The DSP Status flags are inputs to the Interrupt control circuit and can be used to trigger an interrupt

event - see “Interrupts”.

The DSP Status flags can be output directly on a GPIO pin as an external indication of the DSP

Status. See “General Purpose Input / Output” to configure a GPIO pin for this function.

The DSP_IRQn_STS fields are read-only bits. These bits can be set (or reset) by writing to the

DSP_IRQn fields, as described in Table 16. This facility can be used to allow the DSP core to

generate an interrupt to the host processor. The DSP interrupt registers are asserted on the rising and

falling edges of the respective DSP_IRQn fields.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3393

(0D41h)

ADSP2

IRQ0

DSP_IRQ2

DSP IRQ2

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ2_EINTn

interrupt to the host processor.

DSP_IRQ1

DSP IRQ1

0 = Not asserted

1 = Asserted

This bit can be set/reset by a DSP core in

order to generate a DSP_IRQ1_EINTn

interrupt to the host processor.

Table 16 DSP Interrupts

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