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WM5102 Datasheet(PDF) 86 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 86 Page - Wolfson Microelectronics plc |
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86 / 334 page ![]() WM5102 Production Data w PD, June 2014, Rev 4.2 86 DIGITAL CORE DSP The digital core incorporates a programmable DSP block, as illustrated in Figure 33. The DSP supports 8 inputs (Left, Right, Aux1, Aux2, … Aux6). A 4-input mixer is associated with the Left and Right inputs, providing further expansion of the number of input paths. Each of the input sources is selectable, and independent volume control is provided for Left and Right input mixer channels. The DSP block supports 6 outputs. The functionality of the DSP is not fixed, and a wide range of audio enhancements algorithms may be performed. The procedure for configuring the WM5102 DSP functions is tailored to each customer’s application; please contact your local Wolfson representative for more details. For details of the DSP Firmware requirements relating to clocking, register access, and code execution, refer to the “DSP Firmware Control” section. Figure 33 Digital Core DSP Block The DSP1 mixer / input control registers (see Figure 33) are located at register addresses R2368 (940h) through to R2383 (094Fh). The full list of digital mixer control registers is provided in the “Register Map” section (Register R1600 through to R2920). Generic register definitions are provided in Table 7. The *_SRCn registers select the input source(s) for the DSP1 block. Note that the selected input source(s) must be configured for the same sample rate as the DSP to which they are connected. Sample rate conversion functions are available to support flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous Sample Rate Converter (ISRC)”. The bracketed numbers in Figure 33, eg. “(68h)” indicate the corresponding *_SRCn register setting for selection of that signal as an input to another digital core function. The sample rate of the DSP input/output is configured using the DSP1_RATE register - see Table 21. Sample rate conversion is required when routing the DSP1 signal paths to any signal chain that is asynchronous and/or configured for a different sample rate. |
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