TMS320C6711 datasheet(104/129 Pages) TI

104 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

104

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MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP†‡ (see Figure 50) [C6711C/C6711D]

NO.

GDPA-167

−200

−250 (6711D)

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

2P§

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

0.5 * tc(CKRX) −1¶

Setup time external FSR high before CLKR low

CLKR int

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR ext

Hold time external FSR high after CLKR low

CLKR int

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR ext

Setup time DR valid before CLKR low

CLKR int

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR ext

Hold time DR valid after CLKR low

CLKR int

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR ext

Setup time external FSX high before CLKX low

CLKX int

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX ext

Hold time external FSX high after CLKX low

CLKX int

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX ext

† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

§ The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for

communications between the McBSP and other devices is 75 Mbps for 167-MHz and 200-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;

where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The

maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle

time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 15 ns as the minimum

CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =

33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port

is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0)

in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.

¶ This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

TMS320C6711 Datasheet(PDF) 104 Page - Texas Instruments

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