TMS320DM642 datasheet(131/178 Pages) TI

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5.12.3

PCI Electrical Data/Timing

PCLK

0.4 DVDD V MIN

Peak to Peak for

3.3V signaling

PRST

PCLK

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

5.12.3.1

Peripheral Component Interconnect (PCI) Timing

Table 5-42. Timing Requirements for PCLK

(1) (2) (see Figure 5-46)

–500, A-600

–600, –720

[33 MHz]

[66 MHz]

NO.

UNIT

MIN

MAX

MIN

MAX

tc(PCLK)

Cycle time, PCLK

30 (or 4P(3))

15 (or 4P(3))

tw(PCLKH)

Pulse duration, PCLK high

tw(PCLKL)

Pulse duration, PCLK low

tsr(PCLK)

∆v/∆t slew rate, PCLK

1.5

V/ns

(1)

For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN.

(2)

P = 1/CPU clock frequency in ns. For example when running parts at 720 MHz,use P = 1.39 ns.

(3)

Select the parameter value, whichever is larger.

Figure 5-46. PCLK Timing

Table 5-43. Timing Requirements for PCI Reset (see Figure 5-47)

–500

–600

NO.

UNIT

–720

MIN

MAX

tw(PRST)

Pulse duration, PRST

tsu(PCLKA-PRSTH)

Setup time, PCLK active before PRST high

100

µs

Figure 5-47. PCI Reset (PRST) Timing

DM642 Peripheral Information and Electrical Specifications

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TMS320DM642 Datasheet(PDF) 131 Page - Texas Instruments

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