TMS320DM642 datasheet(158/178 Pages) TI

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MRCLK (Input)

MRXD3−MRXD0,

MRXDV, MRXER (Inputs)

MTCLK (Input)

MTXD3−MTXD0,

MTXEN (Outputs)

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

Table 5-76. Timing Requirements for EMAC MII Receive 10/100 Mbit/s

(1) (see Figure 5-65)

–500

–600

NO.

UNIT

–720

MIN

MAX

tsu(MRXD-MRCLKH)

Setup time, receive selected signals valid before MRCLK high

th(MRCLKH-MRXD)

Hold time, receive selected signals valid after MRCLK high

(1)

Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.

Figure 5-65. EMAC Receive Interface Timing

Table 5-77. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit

10/100 Mbit/s

(1) (see Figure 5-66)

–500

–600

NO.

UNIT

–720

MIN

MAX

td(MTCLKH-MTXD)

Delay time, MTCLK high to transmit selected signals valid

(1)

Transmit selected signals include: MTXD3–MTXD0, and MTXEN.

Figure 5-66. EMAC Transmit Interface Timing

158

DM642 Peripheral Information and Electrical Specifications

TMS320DM642 Datasheet(PDF) 158 Page - Texas Instruments

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