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DS26401 Datasheet(PDF) 71 Page - Dallas Semiconductor

Part # DS26401
Description  Octal T1/E1/J1 Framer
PDF  309 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS26401 Datasheet(HTML) 71 Page - Dallas Semiconductor

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DS26401 Octal T1/E1/J1 Framer
71
8.11.5 Receive-Signaling Reinsertion at RSER
In this mode, the user provides a multiframe sync at the RSYNC pin, and the signaling data is reinserted based on
this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The original
signaling data is based on the Fs/ESF frame positions and the realigned data is based on the user-supplied
multiframe sync applied at RSYNC. In voice channels, this extra copy of signaling data is of little consequence.
Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion,
the elastic store must be enabled, however, the backplane clock can be either 1.544MHz or 2.048MHz.
Signaling reinsertion mode is enabled on a per-channel basis by setting the receive-signaling reinsertion channel-
select bit high in the RSIx registers. The channels that are to have signaling reinserted are selected by writing to the
RSI1–RSI3 registers for T1.
8.11.6 Force Receive-Signaling All Ones
In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to 1. This is done by
using the RSAOI registers. The user sets the channel-select bit in the RSAOI1–RSAOI3 registers to select the
channels that are to have the signaling forced to 1.
8.11.7 Receive-Signaling Freeze
The signaling data in the four-multiframe signaling buffer is frozen in a known good state upon either a loss-of-
synchronization (OOF event), carrier loss, or change-of-frame alignment. This action meets the requirements of
BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE control bit
(RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2) high. The
RSIGF output pin provides a hardware indication that a freeze is in effect. The four-multiframe buffer provides a
three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if receive-signaling
reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data is held in the last known good state
until the corrupting error condition subsides. When the error condition subsides, the signaling data is held in the old
state for at least an additional 9ms (or 4.5ms in D4 framing mode) before being allowed to be updated with new
signaling data.



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