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DS26401 Datasheet(PDF) 9 Page - Dallas Semiconductor |
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DS26401 Datasheet(HTML) 9 Page - Dallas Semiconductor |
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9 / 309 page ![]() DS26401 Octal T1/E1/J1 Framer 9 2.3 HDLC Controllers § HDLC Engine (One per Framer): § Independent 64-byte Rx and Tx Buffers with Interrupt Support § Access FDL, Sa, or Single DS0 Channel § Compatible with Polled or Interrupt Driven Environments 2.4 Test and Diagnostics § Global, Full-Feature BERT Any Pseudo-Random Pattern Up to 2 32 - 1 Up to 32 Taps can be Used Simultaneously User-Defined Repetitive Patterns Up to 512 Bytes in Length Large, 48-Bit Error and Bit Counters Map to Any Framer/DS0/FDL (T1) or Sa Bits (E1) § Programmable Error Insertion § BPV Insertion § F-Bit Corruption for Line Testing § Loopbacks Remote Local Per-Channel § IEEE 1149.1 Support 2.5 Control Port § 8-Bit Parallel Control Port § Intel or Motorola Nonmultiplexed Support § Flexible Status Registers Support Polled, Interrupt, or Hybrid Program Environments § Software Reset Supported § Hardware Reset Pin |
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