DS26401 datasheet(43/309 Pages) DALLAS

43 / 309 page

DS26401 Octal T1/E1/J1 Framer

8.2 T1 Receive Framer Description and Operation

The DS26401 includes eight fully independent DS1/E1 framers. The framers are designed to interface seamlessly

to the line side through an external LIU. Each framer can be individually programmed to accept AMI, B8ZS, HDB3,

or NRZ data. In T1 mode, each framer supports D4 (SF), ESF, and SLC-96 frame formats, and detects/reports

common alarms such as AIS, RAI, LOS, and OOF, as well as AIS-CI and RAI-CI. Performance monitor counters

are maintained for each port, which report bipolar/line-code violations, F-bit/CRC errors, and number of out-of-sync

multiframes.

Each framer has an HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or

the FDL (T1 mode), and has 64-byte FIFO buffers in both the transmit and receive paths.

The HDLC controllers perform the necessary overhead for generating and receiving performance report messages

(PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controllers

automatically generate and detect flags; generate and check the CRC checksum; generate and detect abort

sequences and stuff and destuff zeros; and byte align to the data stream. The FIFO buffers are large enough to

allow a full PRM to be received or transmitted without host intervention.

Other features contained within each framer include a BOC detector with programmable code integration and three

independent 16-bit loop-code detectors. Host interface is simplified with status registers optimized for either

interrupt driven or polled environments. In many cases, status bits are reported in both real-time and latched on

change-of-state with separate bits for each state change. Most latched bits can be mapped to generate an external

interrupt on the INT pin.

Backplane interface is simplified with the inclusion of two-frame elastic-store memories in each of the receive and

transmit paths. These buffers can be used to control slips in asynchronous environments, or rate-adapt from

1.544MHz to 2.048MHz. The DS26401 also supports an interleaved backplane operating at 4.096MHz, 8.192MHz,

or 16.384MHz.

Additional details about the operation of the DS1 framer are included in the register descriptions in this section.

DS26401 Datasheet(PDF) 43 Page - Dallas Semiconductor