DS26401 datasheet(47/309 Pages) DALLAS

47 / 309 page

DS26401 Octal T1/E1/J1 Framer

RCR3

Receive Control Register 3

083h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

IDF

—

RSERC

—

RLB

PLB

FLB

Default

Bit 0 / Framer Loopback (FLB)

0 = loopback disabled

1 = loopback enabled

This loopback is useful in testing and debugging applications. In FLB, the DS26401 loops data from the transmit

side back to the receive side. When FLB is enabled, the following occurs:

1) (T1 mode) An unframed all-ones code is transmitted at TPOS and TNEG.

(E1 mode) Normal data is transmitted at TPOS and TNEG.

2) Data at RPOS and RNEG is ignored.

3) All receive-side signals take on timing synchronous with TCLK instead of RCLK.

Bit 1 / Payload Loopback (PLB)

0 = loopback disabled

1 = loopback enabled

When PLB is enabled, the following occurs:

1) Data is transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK.

2) All the receive-side signals continue to operate normally.

3) The TCHCLK and TCHBLK signals are forced low.

4) Data at the TSER, TDATA, and TSIG pins is ignored.

5) The TLCLK signal becomes synchronous with RCLK instead of TCLK.

FRAMER LOOPBACK

RECEIVE

FRAMER

TRANSMIT

FRAMER

BACKPLANE

I/F

BACKPLANE

I/F

TPOS

TNEG

RPOS

RNEG

RSER

TSER

PAYLOAD LOOPBACK

(CAN BE DONE ON A PER-CHANNEL BASIS)

RECEIVE

FRAMER

TRANSMIT

FRAMER

BACKPLANE

I/F

BACKPLANE

I/F

TPOS

TNEG

RPOS

RNEG

RSER

TSER

DS26401 Datasheet(PDF) 47 Page - Dallas Semiconductor

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