DS26401 datasheet(17/309 Pages) DALLAS

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DS26401 Octal T1/E1/J1 Framer

5. SIGNAL DESCRIPTIONS

5.1 Receive Framer Signals

Signal Name:

RPOS (1–8)

Signal Description:

Receive Positive Data Input

Signal Type:

Input

Sampled on the falling edge of RCLK for bipolar data to be clocked through the receive side framer. Data on RPOS

and RNEG will typically be AMI, B8ZS, or HDB3 format bipolar data. RPOS can be used for unipolar (NRZ) data if

enabled by the Input Data Format bit (IDF) at RCR3.7.

Signal Name:

RNEG (1–8)

Signal Description:

Receive Negative Data Input

Signal Type:

Input

Sampled on the falling edge of RCLK for bipolar data to be clocked through the receive side framer. Data on RPOS

and RNEG will typically be AMI, B8ZS, or HDB3 format bipolar data. The RNEG input should be grounded when the

DS26401 is set to receive unipolar (NRZ) data, enabled by the Input Data Format bit (IDF) at RCR3.7.

Signal Name:

RCLK (1–8)

Signal Description:

Receive Clock

Signal Type:

Input

A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive side framer.

Signal Name:

RSER (1–8)

Signal Description:

Receive Serial Data

Signal Type:

Output

Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled.

Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.

Signal Name:

RSIG (1–8)

Signal Description:

Receive Signaling Output

Signal Type:

Output

Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is

disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.

Signal Name:

RSYNC (1–8)

Signal Description:

Receive Sync

Signal Type:

Input/Output

An extracted pulse, one RCLK wide that identifies either frame or multiframe boundaries. If set to output frame

boundaries then RSYNC can be programmed to output doublewide pulses on signaling frames in T1 mode.

Signal Name:

RSYSCLK (1–8)

Signal Description:

Receive System Clock

Signal Type:

Input

1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz, or 16.384MHz receive backplane clock. Only used when the

receive-side elastic store function is enabled. Should be tied low in applications that do not use the receive-side

elastic store.

DS26401 Datasheet(PDF) 17 Page - Dallas Semiconductor

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