DS26401 datasheet(22/309 Pages) DALLAS

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DS26401 Octal T1/E1/J1 Framer

5.5 Test

Signal Name:

JTRST

Signal Description:

IEEE 1149.1 Test Reset

Signal Type:

Input

JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled

from low to high. This action will set the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal

device operation. JTRST is pulled high internally through a 10k

W resistor operation. If boundary scan is not used,

this pin should be held low.

Signal Name:

JTMS

Signal Description:

IEEE 1149.1 Test Mode Select

Signal Type:

Input

This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined

IEEE 1149.1 states. This pin has a 10k

W pullup resistor.

Signal Name:

JTCLK

Signal Description:

IEEE 1149.1 Test Clock Signal

Signal Type:

Input

This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.

Signal Name:

JTDI

Signal Description:

IEEE 1149.1 Test Data Input

Signal Type:

Input

Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k

W pullup resistor.

Signal Name:

JTDO

Signal Description:

IEEE 1149.1 Test Data Output

Signal Type:

Output

Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left

unconnected.

DS26401 Datasheet(PDF) 22 Page - Dallas Semiconductor

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