DS26401 datasheet(97/309 Pages) DALLAS

97 / 309 page

DS26401 Octal T1/E1/J1 Framer

RLS5

Receive Latched Status Register 5 (HDLC)

094h + (200h x n) : where n = 0 to 7, or Ports 1 to 8

Bit #

Name

—

ROVR

RHOBT

RPE

RPS

RHWMS

RNES

Default

Note: All bits in this register are latched and can cause interrupts.

Bit 0 / Receive-FIFO Not Empty Set Event (RNES).

Set when the receive FIFO has transitioned from ‘empty’ to

‘not-empty’ (at least one byte has been put into the FIFO). Rising edge detect of RNE.

Bit 1 / Receive-FIFO Above High-Watermark Set Event (RHWMS).

Set when the receive-64-byte FIFO crosses

the high watermark as defined by the receive HDLC FIFO control register (RHFC). Rising edge detect of RHWM.

Bit 2 / Receive Packet Start Event (RPS).

Set when the HDLC controller detects an opening byte. This is a

latched bit and will be cleared when read.

Bit 3 / Receive Packet End Event (RPE).

Set when the HDLC controller detects either the finish of a valid

message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC

checking error, or an overrun condition, or an abort has been seen. This is a latched bit and is cleared when read.

Bit 4 / Receive HDLC Opening Byte Event (RHOBT).

Set when the next byte available in the receive FIFO is the

first byte of a message.

Bit 5 / Receive FIFO Overrun (ROVR).

Set when the receive HDLC controller has terminated packet reception

because the FIFO buffer is full.

Bits 6, 7 / Unused

DS26401 Datasheet(PDF) 97 Page - Dallas Semiconductor