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DS26401 Datasheet(PDF) 8 Page - Dallas Semiconductor |
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DS26401 Datasheet(HTML) 8 Page - Dallas Semiconductor |
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8 / 309 page  DS26401 Octal T1/E1/J1 Framer 8 2. FEATURES 2.1 Framer/Formatter § Fully Independent Transmit and Receive Functionality § Full Receive and Transmit Path Transparency § T1 Framing Formats D4 and ESF per T1.403, and Expanded SLC-96 Support (TR-TSY-008) § E1 FAS Framing and CRC-4 Multiframe per G.704/G.706 and G.732 CAS Multiframe § Detailed Alarm and Status Reporting with Optional Interrupt Support § Large Path and Line Error Counters for T1: BPV, CV, CRC6, and Framing Bit Errors E1: BPV, CV, CRC4, E-Bit, and Frame Alignment Errors Timed or Manual Update Modes § DS1 Idle Code Generation on a Per-Channel Basis in Both Transmit and Receive Paths User-Defined Digital Milliwatt § ANSI T1.403-1998 Support § G.965 V5.2 Link Detect § Ability to Monitor One DS0 Channel in Both the Transmit and Receive Paths § In-Band Repeating Pattern Generators and Detectors Three Independent Detectors Patterns from 1 to 8 bits or 16 bits in Length § Bit Oriented Code (BOC) Support § Flexible Signaling Support Software- or Hardware-Based Interrupt Generated on Change of Signaling Data Signaling Debounce Optional Receive Signaling Freeze on Loss of Frame (LOF), Loss of Signal (LOS), or Change-of-Frame Alignment § Hardware Pins Provided to Indicate Loss of Frame, Loss of Signal, Loss-of-Transmit Clock (LOTC), or Signaling Freeze Condition § Automatic RAI Generation to ETS 300 011 Specifications § RAI-CI and AIS-CI Support § Expanded Access to Sa and Si Bits § Option to Extend Carrier Loss Criteria to a 1ms Period as per ETS 300 233 § Japanese J1 Support Ability to Calculate and Check CRC6 According to the Japanese Standard Ability to Generate Yellow Alarm According to the Japanese Standard 2.2 System Interface § Independent Two-Frame Receive and Transmit Elastic Stores Independent Control and Clocking Controlled Slip Capability with Status Minimum Delay Mode Supported § Maximum Backplane Rate of 16.384MHz in IBO Mode § Supports T1 to E1 Conversion § Programmable Output Clocks for Fractional T1, E1, H0, and H12 Applications § Interleaving PCM Bus Operation (IBO) § Hardware Signaling Capability Receive Signaling Reinsertion to a Backplane Multiframe Sync Availability of Signaling in a Separate PCM Data Stream Signaling Freezing § Ability to Pass the T1 F-Bit Position Through the Elastic Stores in the 2.048MHz Backplane Mode § User-Selectable Synthesized Clock Output |
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