DS26401 datasheet(52/309 Pages) DALLAS

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DS26401 Octal T1/E1/J1 Framer

8.7 T1 Receive Status and Information

When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1.

Status bits can operate in either a latched or real-time fashion. Some latched bits can be enabled to generate a

hardware interrupt through the INT signal.

Real-Time Bits

Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm

or a condition. Real-time bits remain stable and valid during the host read operation. The current value of the

internal status signals can be read at any time from the real-time status registers without changing any of the

latched status register bits.

Latched Bits

When an event or an alarm occurs and a latched bit is set to 1, it remains set until the user clears it. These bits

typically respond on a change-of-state for an alarm, condition, or event, and operate in a read-then-write fashion.

The user should read the value of the desired status bit and then write a 1 to that particular bit location to clear the

latched value (write a zero to locations not to be cleared). Once the bit is cleared, it is not set again until the event

has occurred again.

Mask Bits

Some of the alarms and events can be either masked or unmasked from the interrupt pin through the interrupt

mask registers (RIMx). When unmasked, the INT signal is forced low when the enabled event or condition occurs.

The INT pin is allowed to return high (if no other unmasked interrupts are present) when the user reads, then clears

(with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin clear

even if the alarm is still present.

Note that some conditions can have multiple status indications. For example, receive loss-of-frame (RLOF)

provides the following indications:

RRTS1.0

(RLOF)

Real-time indication that the receiver is not

synchronized with incoming data stream. Read-only

bit that remains high as long as the condition is

present.

RLS1.0

(RLOFD)

Latched indication that the receiver has lost

synchronization since the bit was last cleared. Bit will

clear when written by the user, even if the condition

is still present (rising edge detect of RRTS1.0).

RLS1.4

(RLOFC)

Latched indication that the receiver has reacquired

synchronization since the bit was last cleared. Bit will

clear when written by the user, even if the condition

is still present (falling edge detect of RRTS1.0).

DS26401 Datasheet(PDF) 52 Page - Dallas Semiconductor

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