TDA2EX datasheet(138/391 Pages) TI1

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TDA2EG-17

SPRS969B – AUGUST 2016 – REVISED JUNE 2017

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Specifications

(11) P = 1/(SYS_CLK1/610) frequency in ns.

Figure 5-5. Power-Down Sequencing

(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.

(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.

(3) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.

(4) vdd must ramp after or at the same time as vdd_dsp.

(5) If any of the vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can

be combined with vdds18v.

–

vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] is allowed to ramp down at either of the two points shown in the timing diagram

in either 1.8V mode or in 3.3V mode.

–

If vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] ramps down at the later time in the diagram then the board design must

guarantee that the vddshv[1-7,9-11] rail is never higher than 2.0 V above the vdds18v rail.

(6) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp

down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other

vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.

(7) Ramped Down is defined as reaching a voltage level of no more than 0.6V.

Figure 5-6 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.

TDA2EX Datasheet(PDF) 138 Page - Texas Instruments